Helmut Reinig - researchr alias

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Viewing Publication 1 - 17 from 17

2014

Deterministic Synthesis of Hybrid Application-Specific Network-on-Chip TopologiesVladimir Todorov, Daniel Mueller-Gritschneder, Helmut Reinig, Ulf Schlichtmann. tcad, 33(10):1503-1516, 2014. [doi]

2013

A spectral clustering approach to application-specific network-on-chip synthesisVladimir Todorov, Daniel Mueller-Gritschneder, Helmut Reinig, Ulf Schlichtmann. date 2013: 1783-1788 [doi]

2012

Automated construction of a cycle-approximate transaction level model of a memory controllerVladimir Todorov, Daniel Mueller-Gritschneder, Helmut Reinig, Ulf Schlichtmann. date 2012: 1066-1071 [doi]

Non-intrusive trace & debug noc architecture with accurate timestamping for GALS SoCsVladimir Todorov, Alberto Ghiribaldi, Helmut Reinig, Davide Bertozzi, Ulf Schlichtmann. codes 2012: 181-186 [doi]

2011

Contrasting multi-synchronous MPSoC design styles for fine-grained clock domain partitioning: the full-HD video playback case studyHervé Tatenguem, Daniele Ludovici, Alessandro Strano, Davide Bertozzi, Helmut Reinig. micro 2011: 37-42 [doi]

2010

Comparison of Deadlock Recovery and Avoidance Mechanisms to Approach Message Dependent Deadlocks in On-chip NetworksAndreas Lankes, Thomas Wild, Andreas Herkersdorf, Sören Sonntag, Helmut Reinig. nocs 2010: 17-24 [doi]

2009

NoC topology exploration for mobile multimedia applicationsAndreas Lankes, Andreas Herkersdorf, Sören Sonntag, Helmut Reinig. icecsys 2009: 707-710 [doi]

2008

An Efficient Weighted-Round-Robin Algorithm for Multiprocessor ArchitecturesSören Sonntag, Helmut Reinig. anss 2008: 193-199 [doi]

1999

A scalable architecture for custom computingHelmut Reinig. PhD thesis, Universität Kaiserslautern, 1999.

1998

Codevelopment of long haul ISDN transceiver and design methodology improves time to marketMarkus Brandstetter, Torsten Harms, Helmut Reinig, Michael Vanrompay. icecsys 1998: 407-410 [doi]

1996

CoDe-C: A Novel Two-Level Hardware/Software Co-Design FrameworkReiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig. vlsid 1996: 81-84 [doi]

High-performance computing using a reconfigurable acceleratorReiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig. concurrency, 8(6):429-443, 1996.

1995

A Parallelizing Compilation Method for the Map-oriented MachineReiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig, Karin Schmidt. asap 1995: 129-132 [doi]

1994

Data-Procedural Languages for FPL-based MachinesAndreas Ast, Jürgen Becker, Reiner W. Hartenstein, Rainer Kress, Helmut Reinig, Karin Schmidt. fpl 1994: 183-195

A New FPGA Architecture for Word-Oriented DatapathsReiner W. Hartenstein, Rainer Kress, Helmut Reinig. fpl 1994: 144-155

A dynamically reconfigurable wavefront array architecture for evaluation of expressionsReiner W. Hartenstein, Rainer Kress 0002, Helmut Reinig. asap 1994: 404-414 [doi]

1992

Novel High Performance Machine Paradigms and Fast- Turnaround ASIC Design MethodsAndreas Ast, Reiner W. Hartenstein, Rainer Kress, Helmut Reinig, Karin Schmidt. fpga 1993: 211-217

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