Abstract is missing.
- Fast linear Hough transformJean Vuillemin. 1-9 [doi]
- Algorithms and architectures for hierarchical compression of videoMohan Vishwanath. 10-21 [doi]
- A high performance IIR filter chip and its evaluation systemRichard L. Walke, Roger Evans, Roger F. Woods, G. Floyd, K. W. Wood. 22-32 [doi]
- Automated design of DSP array processor chipsJohn V. McCanny, Yi Hu, M. Yan. 33-44 [doi]
- Behavioral synthesis of high performance, low cost, and low power application specific processors for linear computationsMiodrag Potkonjak, Mani B. Srivastava. 45-56 [doi]
- Distributed control synthesis for data-dependent iterative algorithmsBongjin Jung, Yongjin Jeong, Wayne P. Burleson. 57-68 [doi]
- Rapid prototyping with programmable control pathsRaminder Singh Bajwa, Chetana N. Keltcher, Paul Keltcher, Mary Jane Irwin. 69-74 [doi]
- Minimizing memory requirements in rate-optimal schedulesRamaswamy Govindarajan, Guang R. Gao, Palash Desai. 75-86 [doi]
- A methodology for performance prediction of Sphinx I in multi-computer architecturesCarol Hernandez, Daniel P. Siewiorek, Zary Segall. 87-98 [doi]
- Optimal synthesis of application specific heterogeneous pipelined multiprocessorsJ. C. DeSouza-Batista, Alice C. Parker. 99-110 [doi]
- Register transfer modeling and simulation for array processorsW. H. Chou, Sun-Yuan Kung. 111-122 [doi]
- A systolic array for 2-D DFT and 2-D DCTHyesook Lim, Earl E. Swartzlander Jr.. 123-131 [doi]
- Analog VLSI arrays for morphological image processingTonia G. Morris, Stephen P. DeWeerth. 132-142 [doi]
- A fast pipelined FFT unitLuca Breveglieri, Vincenzo Piuri. 143-151 [doi]
- Parallel architectures for computing the Hough transform and CT image reconstructionLei Lin, Vijay K. Jain. 152-163 [doi]
- Verification of regular architectures using ALPHA: a case studyC. Dezan, Patrice Quinton. 164-175 [doi]
- A processor-time-minimal schedule for the standard tensor product algorithmChris J. Scheiman, Peter R. Cappello. 176-187 [doi]
- A processor for calorimetry at the Large Hadron Collider in the FERMI projectLuigi Dadda, Sami J. Inkinen, Vincennzo Ncenzo Piuri. 188-199 [doi]
- Regular array synthesis using ALPHADoran K. Wilde, Oumarou Sie. 200-211 [doi]
- Data compiling for systems of affine recurrence equationsCatherine Mongenet. 212-223 [doi]
- Optimal mapping of systolic algorithms by regular instruction shiftsPhilippe Clauss, Guy-René Perrin. 224-235 [doi]
- On the injectivity of modular mappingsHyuk-Jae Lee, José A. B. Fortes. 236-247 [doi]
- A variable-precision interval arithmetic processorMichael J. Schulte, Earl E. Swartzlander Jr.. 248-258 [doi]
- Architectures for lattice structure based orthonormal discrete wavelet transformsTracy C. Denk, Keshab K. Parhi. 259-270 [doi]
- A data path array with shared memory as core of a high performance DSPJohannes Kneip, Karsten Rönner, Peter Pirsch. 271-282 [doi]
- Synthesis of a class of data format converters with specified delaysJongwoo Bae, Vilttor K. Prasanna, Heonchul Park. 283-294 [doi]
- Designing systolic arrays for integer GCD computationTudor Jebelean. 295-301 [doi]
- A sparse knapsack algo-tech-cuit and its synthesisRumen Andonov, Sanjay V. Rajopadhye. 302-313 [doi]
- A parallel system for photo realistic artificial scene renderingEd F. Deprettere, Gerben J. Hekstra, Li-Sheng Shen, Jichun Bu, Gerrit Boersma. 314-323 [doi]
- Parallel processing of complex data using quaternion and pseudo-quaternion CORDIC algorithmsShen-Fu Hsiao, Jean-Marc Delosme. 324-335 [doi]
- A SIMD solution to the sequence comparison problem on the MGAPManjit Borah, Raminder Singh Bajwa, Sridhar Hannenhalli, Mary Jane Irwin. 336-345 [doi]
- Access and alignment of arrays for a bidimensional parallel memoryCéline Verdier, Emmanuel Boutillon, Anne Lafage, Alain Demeure. 346-356 [doi]
- Constant-time triangulation problems on reconfigurable meshesVenkatavasu Bokka, Himabindu Gurla, Stephan Olariu, James L. Schwing. 357-368 [doi]
- A scalable bit-sequential SIMD array for nearest-neighbor classification using the city-block metricMartin Neschen. 369-380 [doi]
- A parallel DSP-based neural network emulator with CMOS VLSI packet switching hardwareMarkus Schwarz, Bedrich J. Hosticka, M. Kesper, Peter Richert, Michael Scholles. 381-391 [doi]
- An efficient VLSI architecture for digital geometryRong Lin, Stephan Olariu, James L. Schwing. 392-403 [doi]
- A dynamically reconfigurable wavefront array architecture for evaluation of expressionsReiner W. Hartenstein, Rainer Kress 0002, Helmut Reinig. 404-414 [doi]
- An optimisation methodology for array mapping of affine recurrence equations in video and image processingJan Rosseel, Francky Catthoor, Hugo De Man. 415-426 [doi]
- Loop transformation methodology for fixed-rate video, image and telecom processing applicationsFrancky Catthoor, Werner Geurts, Hugo De Man. 427-438 [doi]
- Data alignment of loop nests without nonlocal communicationsWeijia Shang, Zhongliang Shu. 439-450 [doi]