Abstract is missing.
- Low-Power Bioelectronics for Massively Parallel NeuromonitoringMohamad Sawan. 3 [doi]
- Photonic Chip-Scale Interconnection Networks for Performance-Energy Optimized ComputingKeren Bergman. 4 [doi]
- Semiconductor Industry: Perspective, Evolution and ChallengesAlessandro Cremonesi. 5 [doi]
- Evaluating Bufferless Flow Control for On-chip NetworksGeorge Michelogiannakis, Daniel Sanchez, William J. Dally, Christos Kozyrakis. 9-16 [doi]
- Comparison of Deadlock Recovery and Avoidance Mechanisms to Approach Message Dependent Deadlocks in On-chip NetworksAndreas Lankes, Thomas Wild, Andreas Herkersdorf, Sören Sonntag, Helmut Reinig. 17-24 [doi]
- Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant RoutingSamuel Rodrigo, Jose Flich, Antoni Roca, Simone Medardoni, Davide Bertozzi, J. Camacho, Federico Silla, José Duato. 25-32 [doi]
- Improving the Performance of GALS-Based NoCs in the Presence of Process VariationCarles Hernandez, Antoni Roca, Federico Silla, Jose Flich, José Duato. 35-42 [doi]
- A Low-Overhead Asynchronous Interconnection Network for GALS Chip MultiprocessorsMichael N. Horak, Steven M. Nowick, Matthew Carlberg, Uzi Vishkin. 43-50 [doi]
- Asynchronous Bypass Channels: Improving Performance for Multi-synchronous NoCsTushar N. K. Jain, Paul V. Gratz, Alex Sprintson, Gwan Choi. 51-58 [doi]
- Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPsHiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano. 61-68 [doi]
- Design of a High-Throughput Distributed Shared-Buffer NoC RouterRohit Sunkam Ramanujam, Vassos Soteriou, Bill Lin, Li-Shiuan Peh. 69-78 [doi]
- Fault-Tolerant Flow Control in On-chip NetworksYoung Hoon Kang, Taek-Jun Kwon, Jeffrey T. Draper. 79-86 [doi]
- A 128 x 128 x 24Gb/s Crossbar Interconnecting 128 Tiles in a Single Hop and Occupying 6 of Their AreaGiorgos Passas, Manolis Katevenis, Dionisios N. Pnevmatikatos. 87-95 [doi]
- A Low-Latency and Memory-Efficient On-chip NetworkMasoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen. 99-106 [doi]
- Temperature-Aware Delay Borrowing for Energy-Efficient Low-Voltage Link DesignDavid Wolpert, Bo Fu, Paul Ampadu. 107-114 [doi]
- Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCsDaniel Gebhardt, JunBok You, Kenneth S. Stevens. 115-122 [doi]
- Physical-Aware Link Allocation and Route Assignment for Chip MultiprocessingNikita Nikitin, Satrajit Chatterjee, Jordi Cortadella, Michael Kishinevsky, Ümit Y. Ogras. 125-134 [doi]
- Network-on-Chip Architectures for Neural NetworksDmitri Vainbrand, Ran Ginosar. 135-144 [doi]
- Transient and Permanent Error Co-management Method for Reliable Networks-on-ChipQiaoyan Yu, Paul Ampadu. 145-154 [doi]
- Back Suction: Service Guarantees for Latency-Sensitive On-chip NetworksJonas Diemer, Rolf Ernst. 155-162 [doi]
- Improved Utilization of NoC Channel Bandwidth by Switch Replication for Cost-Effective Multi-processor Systems-on-ChipFrancisco Gilabert Villamón, María Engracia Gómez, Simone Medardoni, Davide Bertozzi. 165-172 [doi]
- Physical vs. Virtual Express Topologies with Low-Swing Links for Future Many-Core NoCsChia-Hsin Owen Chen, Niket Agarwal, Tushar Krishna, Kyung-Hoae Koo, Li-Shiuan Peh, Krishna Saraswat. 173-180 [doi]
- Design of High-Radix Clos Network-on-ChipYu-Hsiang Kao, Najla Alfaraj, Ming Yang, H. Jonathan Chao. 181-188 [doi]
- Hierarchical Network-on-Chip for Embedded Many-Core ArchitecturesAlexandre Guerre, Nicolas Ventroux, Raphael David, Alain Mérigot. 189-196 [doi]
- A Low-Cost Deadlock-Free Design of Minimal-Table Rerouted XY-Routing for Irregular Wireless NoCsRuizhe Wu, Yi Wang, Dan Zhao. 199-206 [doi]
- Power-Efficient and High-Performance Multi-level Hybrid Nanophotonic Interconnect for MulticoresRandy Wayne Morris Jr., Avinash Karanth Kodi. 207-214 [doi]
- Performance Evaluation of a Multicore System with Optically Connected Memory ModulesPaul Vincent Mejia, Rajeevan Amirtharajah, Matthew K. Farrens, Venkatesh Akella. 215-222 [doi]
- Traffic- and Thermal-Aware Run-Time Thermal Management Scheme for 3D NoC SystemsChih-Hao Chao, Kai-Yuan Jheng, Hao-Yu Wang, Jia-Cheng Wu, An-Yeu Wu. 223-230 [doi]
- Distributed Sequencing for Resource Sharing in Multi-applicative Heterogeneous NoC PlatformsYvain Thonnart, Romain Lemaire, Fabien Clermidy. 233-240 [doi]
- QuaLe: A Quantum-Leap Inspired Model for Non-stationary Analysis of NoC Traffic in Chip Multi-processorsPaul Bogdan, Miray Kas, Radu Marculescu, Onur Mutlu. 241-248 [doi]
- Impact of Half-Duplex and Full-Duplex DMA Implementations on NoC PerformanceFrancesca Palumbo, Danilo Pani, Alessandro Pilia, Luigi Raffo. 249-256 [doi]
- A Network Congestion-Aware Memory ControllerDongki Kim, Sungjoo Yoo, Sunggu Lee. 257-264 [doi]