Abstract is missing.
- Smart systems for internet of thingsBenedetto Vigna. 1 [doi]
- Creating a sustainable information and communication infrastructureMassoud Pedram. 2 [doi]
- Optimized out-of-order parallel discrete event simulation using predictionsWeiwei Chen, Rainer Dömer. 3-8 [doi]
- Parallel programming with SystemC for loosely timed models: a non-intrusive approachMatthieu Moy. 9-14 [doi]
- Accuracy vs speed tradeoffs in the estimation of fixed-point errors on linear time-invariant systemsDavid Novo, Sara El Alaoui, Paolo Ienne. 15-20 [doi]
- Runtime verification of nonlinear analog circuits using incremental time-augmented RRT algorithmSeyed Nematollah Ahmadyan, Jayanand Asok Kumar, Shobha Vasudevan. 21-26 [doi]
- An automated parallel simulation flow for heterogeneous embedded systemsSeyed Hosein Attarzadeh Niaki, Ingo Sander. 27-30 [doi]
- Mutation analysis with coverage discountingPeter Lisherness, Nicole Lesperance, Kwang-Ting (Tim) Cheng. 31-34 [doi]
- Scalable fault localization for SystemC TLM designsHoang M. Le, Daniel Große, Rolf Drechsler. 35-38 [doi]
- Cherry-picking: exploiting process variations in dark-silicon homogeneous chip multi-processorsBharathwaj Raghunathan, Yatish Turakhia, Siddharth Garg, Diana Marculescu. 39-44 [doi]
- Energy optimization with worst-case deadline guarantee for pipelined multiprocessor systemsGang Chen, Kai Huang, Christian Buckl, Alois Knoll. 45-50 [doi]
- Self-adaptive hybrid dynamic power management for many-core systemsMuhammad Shafique, Benjamin Vogel, Jörg Henkel. 51-56 [doi]
- SmartCap: user experience-oriented power adaptation for smartphone's application processorXueliang Li, Guihai Yan, Yinhe Han, Xiaowei Li 0001. 57-60 [doi]
- Runtime power estimation of mobile AMOLED displaysDongwon Kim, Wonwoo Jung, Hojung Cha. 61-64 [doi]
- AVICA: an access-time variation insensitive L1 cache architectureSeokin Hong, Soontae Kim. 65-70 [doi]
- Dual-addressing memory architecture for two-dimensional memory access patternsYen-Hao Chen, Yi-Yu Liu. 71-76 [doi]
- Adaptive cache management for a combined SRAM and DRAM cache hierarchy for multi-coresFazal Hameed, Lars Bauer, Jörg Henkel. 77-82 [doi]
- Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modesVicente Lorente, Alejandro Valero, Julio Sahuquillo, Salvador Petit, Ramon Canal, Pedro López, José Duato. 83-88 [doi]
- A dual grain hit-miss detector for large die-stacked DRAM cachesMichel El-Nacouzi, Islam Atta, Myrto Papadopoulou, Jason Zebchuk, Natalie D. Enright Jerger, Andreas Moshovos. 89-92 [doi]
- Reducing writes in phase-change memory environments by using efficient cache replacement policiesRoberto Rodríguez-Rodríguez, Fernando Castro, Daniel Chaver, Luis Piñuel, Francisco Tirado. 93-96 [doi]
- Low complexity QR-decomposition architecture using the logarithmic number systemJochen Rust, Frank Ludwig, Steffen Paul. 97-102 [doi]
- Perceptual quality preserving SRAM architecture for color motion picturesWen Yueh, Minki Cho, Saibal Mukhopadhyay. 103-108 [doi]
- Parameterized area-efficient multi-standard turbo decoderPurushotham Murugappa, Amer Baghdadi, Michel Jézéquel. 109-114 [doi]
- An H.264 Quad-FullHD low-latency intra video encoderMuhammad Usman Karim Khan, Jan Micha Borrmann, Lars Bauer, Muhammad Shafique, Jörg Henkel. 115-120 [doi]
- A 100 GOPS ASP based baseband processor for wireless communicationZiyuan Zhu, Shan Tang, Yongtao Su, Juan Han, Gang Sun, Jinglin Shi. 121-124 [doi]
- Hardware-software collaborative complexity reduction scheme for the emerging HEVC intra encoderMuhammad Usman Karim Khan, Muhammad Shafique, Mateus Grellert, Jörg Henkel. 125-128 [doi]
- Reliability challenges of real-time systems in forthcoming technology nodesSaid Hamdioui, Michael Nicolaidis, Dimitris Gizopoulos, Arnaud Grasset, Groeseneken Guido, Philippe Bonnot. 129-134 [doi]
- Sensitivity analysis for arbitrary activation patterns in real-time systemsMoritz Neukirchner, Sophie Quinton, Tobias Michaels, Philip Axer, Rolf Ernst. 135-140 [doi]
- PT-AMC: integrating preemption thresholds into mixed-criticality schedulingQingling Zhao, Zonghua Gu, Haibo Zeng. 141-146 [doi]
- An elastic mixed-criticality task model and its scheduling algorithmHang Su, Dakai Zhu. 147-152 [doi]
- An open platform for mixed-criticality real-time ethernetGonzalo Carvajal, Sebastian Fischmeister. 153-156 [doi]
- Modular SoC integration with subsystems: the audio subsystem casePieter van der Wolf, Ruud Derwig. 157-162 [doi]
- Configurability in IP subystems: baseband examplesPierre-Xavier Thomas, Grant Martin, David Heine, Dennis Moolenaar, James Kim. 163-168 [doi]
- Configurable I/O integration to reduce system-on-chip time to market: DDR, PCIe examplesFrank Martin, Peter Bennett. 169 [doi]
- High-performance imaging subsystems and their integration in mobile devicesMenno Lindwer, Mark Ruvald Pedersen. 170 [doi]
- Panel: the heritage of Mead & Conway: what has remained the same, what was missed, what has changed, what lies aheadMarco Casale-Rossi, Alberto L. Sangiovanni-Vincentelli, Luca P. Carloni, Bernard Courtois, Hugo De Man, Antun Domic, Jan M. Rabaey. 171-175 [doi]
- Profit maximization through process variation aware high level synthesis with speed binningMengying Zhao, Alex Orailoglu, Chun Jason Xue. 176-181 [doi]
- Instruction-set extension under process variation and aging effectsYuko Hara-Azumi, Farshad Firouzi, Saman Kiamehr, Mehdi Baradaran Tahoori. 182-187 [doi]
- Multispeculative additive trees in high-level synthesisAlberto A. Del Barrio, Román Hermida, Seda Ogrenci Memik, Jose Manuel Mendias, María C. Molina. 188-193 [doi]
- Multi-pumping for resource reduction in FPGA high-level synthesisAndrew Canis, Jason Helge Anderson, Stephen Dean Brown. 194-197 [doi]
- Resource-constrained high-level datapath optimization in ASIP designYuankai Chen, Hai Zhou. 198-201 [doi]
- Extracting useful computation from error-prone processors for streaming applicationsYavuz Yetim, Margaret Martonosi, Sharad Malik. 202-207 [doi]
- Orchestrator: a low-cost solution to reduce voltage emergencies for multi-threaded applicationsXing Hu, Guihai Yan, Yu Hu, Xiaowei Li 0001. 208-213 [doi]
- Memory array protection: check on read or check on write?Panagiota Nikolaou, Yiannakis Sazeides, Lorena Ndreu, Emre Özer, Sachin Idgunji. 214-219 [doi]
- FaulTM: error detection and recovery using hardware transactional memoryGulay Yalcin, Osman S. Unsal, Adrián Cristal. 220-225 [doi]
- Phœnix: reviving MLC blocks as SLC to extend NAND flash devices lifetimeXavier Jimenez, David Novo, Paolo Ienne. 226-229 [doi]
- SCC thermal model identification via advanced bias-compensated least-squaresRoberto Diversi, Andrea Bartolini, Andrea Tilli, Francesco Beneventi, Luca Benini. 230-235 [doi]
- System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMsKarthik Chandrasekar 0001, Christian Weis, Benny Akesson, Norbert Wehn, Kees Goossens. 236-241 [doi]
- Design of low energy, high performance synchronous and asynchronous 64-point FFTWilliam Lee, Vikas S. Vij, Anthony R. Thatcher, Kenneth S. Stevens. 242-247 [doi]
- A multi-level Monte Carlo FPGA accelerator for option pricing in the Heston modelChristian de Schryver, Pedro Torruella, Norbert Wehn. 248-253 [doi]
- Non-speculative double-sampling technique to increase energy-efficiency in a high-performance processorJunyoung Park, Ameya Chaudhari, Jacob A. Abraham. 254-257 [doi]
- User-aware energy efficient streaming strategy for smartphone based video playback applicationsHao Shen, Qinru Qiu. 258-261 [doi]
- Utility-aware deferred load balancing in the cloud driven by dynamic pricing of electricityMuhammad Abdullah Adnan, Rajesh Gupta. 262-265 [doi]
- Leakage and temperature aware server control for improving energy efficiency in data centersMarina Zapater, José Luis Ayala, José Manuel Moya, Kalyan Vaidyanathan, Kenny C. Gross, Ayse Kivilcim Coskun. 266-269 [doi]
- MTTF-balanced pipeline designFabian Oboril, Mehdi Baradaran Tahoori. 270-275 [doi]
- Efficient variation-aware statistical dynamic timing analysis for delay test applicationsMarcus Wagner, Hans-Joachim Wunderlich. 276-281 [doi]
- SlackProbe: a low overhead in situ on-line timing slack monitoring methodologyLiangzhen Lai, Vikas Chandra, Robert C. Aitken, Puneet Gupta. 282-287 [doi]
- Capturing post-silicon variation by layout-aware path-delay testingXiaolin Zhang, Jing Ye, Yu Hu, Xiaowei Li 0001. 288-291 [doi]
- Adaptive reduction of the frequency search space for multi-vdd digital circuitsChandra K. H. Suresh, Ender Yilmaz, Sule Ozev, Ozgur Sinanoglu. 292-295 [doi]
- FIFO cache analysis for WCET estimation: a quantitative approachNan Guan, Xinping Yang, Mingsong Lv, Wang Yi 0001. 296-301 [doi]
- Timing analysis of multi-mode applications on AUTOSAR conform multi-core systemsMircea Negrean, Sebastian Klawitter, Rolf Ernst. 302-307 [doi]
- Bounding SDRAM interference: detailed analysis vs. latency-rate analysisHardik Shah, Alois Knoll, Benny Akesson. 308-313 [doi]
- Role of design in multiple patterning: technology development, design enablement and process controlRani S. Ghaida, Puneet Gupta. 314-319 [doi]
- Overcoming post-silicon validation challenges through quick error detection (QED)David Lin, Ted Hong, Yanjing Li, Farzan Fallah, Donald S. Gardner, Nagib Hakim, Subhasish Mitra. 320-325 [doi]
- Stochastic degradation modeling and simulation for analog integrated circuits in nanometer CMOSGeorges G. E. Gielen, Elie Maricau. 326-331 [doi]
- A transition-signaling bundled data NoC switch architecture for cost-effective GALS multicore systemsAlberto Ghiribaldi, Davide Bertozzi, Steven M. Nowick. 332-337 [doi]
- SMART: a single-cycle reconfigurable NoC for SoC applicationsChia-Hsin Owen Chen, Sunghyun Park, Tushar Krishna, Suvinay Subramanian, Anantha P. Chandrakasan, Li-Shiuan Peh. 338-343 [doi]
- Switch folding: network-on-chip routers with time-multiplexed output portsGiorgos Dimitrakopoulos, N. Georgiadis, Chrysostomos Nicopoulos, Emmanouil Kalligeros. 344-349 [doi]
- An efficient network on-chip architecture based on isolating local and non-local communicationsVahideh Akhlaghi, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram. 350-353 [doi]
- SVR-NoC: a performance analysis tool for network-on-chips using learning-based support vector regression modelZhiliang Qian, Da-Cheng Juan, Paul Bogdan, Chi-Ying Tsui, Diana Marculescu, Radu Marculescu. 354-357 [doi]
- Reliability analysis reloaded: how will we survive?Robert Aitken, Görschwin Fey, Zbigniew T. Kalbarczyk, Frank Reichenbach, Matteo Sonza Reorda. 358-367 [doi]
- MALEC: a multiple access low energy cacheMatthias Boettcher, Giacomo Gabrielli, Bashir M. Al-Hashimi, Danny Kershaw. 368-373 [doi]
- TreeFTL: efficient RAM management for high performance of NAND flash-based storage systemsChundong Wang, Weng-Fai Wong. 374-379 [doi]
- DA-RAID-5: a disturb aware data protection technique for NAND flash storage systemsJie Guo, Wujie Wen, Yaojun Zhang, Sicheng Li, Hai Li, Yiran Chen. 380-385 [doi]
- Exploiting subarrays inside a bank to improve phase change memory performanceJianhui Yue, Yifeng Zhu. 386-391 [doi]
- Future of GPGPU micro-architectural parametersCedric Nugteren, Gert-Jan van den Braak, Henk Corporaal. 392-395 [doi]
- Synchronizing code execution on ultra-low-power embedded multi-channel signal analysis platformsAhmed Yasir Dogan, Ruben Braojos, Jeremy Constantin, Giovanni Ansaloni, Andreas Burg, David Atienza. 396-399 [doi]
- Using synchronization stalls in power-aware acceleratorsAli Jooya, Amirali Baniasadi. 400-403 [doi]
- Comprehensive analysis of software countermeasures against fault attacksNikolaus Theißing, Dominik Merli, Michael Smola, Frederic Stumpf, Georg Sigl. 404-409 [doi]
- An EDA-friendly protection scheme against side-channel attacksAli Galip Bayrak, Nikola Velickovic, Francesco Regazzoni, David Novo, Philip Brisk, Paolo Ienne. 410-415 [doi]
- Design and implementation of a group-based RO PUFChi-En Daniel Yin, Gang Qu, Qiang Zhou. 416-421 [doi]
- ClockPUF: physical unclonable functions based on clock networksYida Yao, MyungBo Kim, Jianmin Li, Igor L. Markov, Farinaz Koushanfar. 422-427 [doi]
- Memristor PUFs: a new generation of memory-based physically unclonable functionsPatrick Koeberl, Ünal Koçabas, Ahmad-Reza Sadeghi. 428-431 [doi]
- Wireless sensor network simulation for security and performance analysisA. Díaz, P. Sanchez, J. Sancho, J. Rico. 432-435 [doi]
- Accurate QBF-based test pattern generation in presence of unknown valuesStefan Hillebrecht, Michael A. Kochte, Dominik Erb, Hans-Joachim Wunderlich, Bernd Becker. 436-441 [doi]
- Test solution for data retention faults in low-power SRAMsLeonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine. 442-447 [doi]
- Efficient SAT-based dynamic compaction and relaxation for longest sensitizable pathsMatthias Sauer, Sven Reimer, Tobias Schubert, Ilia Polian, Bernd Becker. 448-453 [doi]
- Process-variation-aware Iddq diagnosis for nano-scale CMOS designs - the first stepChia-Ling Chang, Charles H.-P. Wen, Jayanta Bhadra. 454-457 [doi]
- Security challenges in automotive hardware/software architecture designFlorian Sagstetter, Martin Lukasiewycz, Sebastian Steinhorst, Marko Wolf, Alexandre Bouard, William R. Harris, Somesh Jha, Thomas Peyrin, Axel Poschmann, Samarjit Chakraborty. 458-463 [doi]
- Experiences with mobile processors for energy efficient HPCNikola Rajovic, Alejandro Rico, James Vipond, Isaac Gelado, Nikola Puzovic, Alex Ramírez. 464-468 [doi]
- What designs for coming supercomputers?Xavier Vigouroux. 469 [doi]
- Energy-efficient in-memory database computingWolfgang Lehner. 470-474 [doi]
- Performance analysis of HPC applications on low-power embedded platformsLuka Stanisic, Brice Videau, Johan Cronsioe, Augustin Degomme, Vania Marangozova-Martin, Arnaud Legrand, Jean-François Méhaut. 475-480 [doi]
- Alternative power supply concepts for self-sufficient wireless sensor nodes by energy harvestingRobert Kappel, Günter Hofer, Gerald Holweg, Thomas Herndl, Günter Hofer, Gerald Holweg. 481 [doi]
- Adaptable, high performance energy harvesters: can energy harvesting deliver enough power for automotive electronics?Paul D. Mitcheson. 482 [doi]
- Ultra-low power: an EDA challengeChristoph Grimm, Javier Moreno, Xiao Pan. 483 [doi]
- DoE-based performance optimization of energy management in sensor nodes powered by tunable energy-harvestersTom J. Kazmierski, Leran Wang, Bashir M. Al-Hashimi, Geoff V. Merrett. 484 [doi]
- A hybrid approach for fast and accurate trace signal selection for post-silicon debugMin Li, Azadeh Davoodi. 485-490 [doi]
- Machine learning-based anomaly detection for post-silicon bug diagnosisAndrew DeOrio, Qingkun Li, Matthew Burgess, Valeria Bertacco. 491-496 [doi]
- Space sensitive cache dumping for post-silicon validationSandeep Chandran, Smruti R. Sarangi, Preeti Ranjan Panda. 497-502 [doi]
- Fast and accurate BER estimation methodology for I/O links based on extreme value theoryAlessandro Cevrero, Nestor E. Evmorfopoulos, Charalampos Antoniadis, Paolo Ienne, Yusuf Leblebici, Andreas Burg, Georgios I. Stamoulis. 503-508 [doi]
- Automated determination of top level control signalsRohit Kumar Jain, Praveen Tiwari, Soumen Ghosh. 509-512 [doi]
- A cache design for probabilistically analysable real-time systemsLeonidas Kosmidis, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla. 513-518 [doi]
- MARTHA: architecture for control and emulation of power electronics and smart grid systemsMichel A. Kinsy, Ivan Celanovic, Omer Khan, Srinivas Devadas. 519-524 [doi]
- Conservative open-page policy for mixed time-criticality memory controllersSven Goossens, Benny Akesson, Kees Goossens. 525-530 [doi]
- An efficient and flexible hardware support for accelerating synchronization operations on the STHORM many-core architectureFarhat Thabet, Yves Lhuillier, Caaliph Andriamisaina, Jean-Marc Philippe, Raphaël David. 531-534 [doi]
- Hot-swapping architecture with back-biased testing for mitigation of permanent faults in functional unit arrayZoltán Endre Rákossy, Masayuki Hiromoto, Hiroshi Tsutsui, Takashi Sato, Yukihiro Nakamura, Hiroyuki Ochi. 535-540 [doi]
- Variation-tolerant OpenMP tasking on tightly-coupled processor clustersAbbas Rahimi, Andrea Marongiu, Paolo Burgio, Rajesh K. Gupta, Luca Benini. 541-546 [doi]
- Accurate and efficient reliability estimation techniques during ADL-driven embedded processor designZheng Wang, Kapil Singh, Chao Chen, Anupam Chattopadhyay. 547-552 [doi]
- Handling discontinuous effects in modeling spatial correlation of wafer-level analog/RF testsKe Huang, Nathan Kupp, John M. Carulli Jr., Yiorgos Makris. 553-558 [doi]
- Fault detection, real-time error recovery, and experimental demonstration for digital microfluidic biochipsKai Hu, Bang-Ning Hsu, Andrew Madison, Krishnendu Chakrabarty, Richard B. Fair. 559-564 [doi]
- Fault analysis and simulation of large scale industrial mixed-signal circuitsEnder Yilmaz, Geoff Shofner, LeRoy Winemberg, Sule Ozev. 565-570 [doi]
- Electrical calibration of spring-mass MEMS capacitive accelerometersLingfei Deng, Vinay Kundur, Naveen Sai Jangala Naga, Muhlis Kenan Ozel, Ender Yilmaz, Sule Ozev, Bertan Bakkaloglu, Sayfe Kiaei, Divya Pratab, Tehmoor Dar. 571-574 [doi]
- Optimizing remote accesses for offloaded kernels: application to high-level synthesis for FPGAChristophe Alias, Alain Darte, Alexandru Plesco. 575-580 [doi]
- Sequentially constructive concurrency: a conservative extension of the synchronous model of computationReinhard von Hanxleden, Michael Mendler, Joaquin Aguado, Björn Duderstadt, Insa Fuhrmann, Christian Motika, Stephen Mercer, Owen O'Brien. 581-586 [doi]
- Fast and accurate cache modeling in source-level simulation of embedded softwareZhonglei Wang, Jörg Henkel. 587-592 [doi]
- Automatic and efficient heap data management for limited local memory multicore architecturesKe Bai, Aviral Shrivastava. 593-598 [doi]
- Software enabled wear-leveling for hybrid PCM main memory on embedded systemsJingtong Hu, Qingfeng Zhuge, Chun Jason Xue, Wei-Che Tseng, Edwin Hsing-Mean Sha. 599-602 [doi]
- Probabilistic timing analysis on conventional cache designsLeonidas Kosmidis, Charlie Curtsinger, Eduardo Quiñones, Jaume Abella, Emery D. Berger, Francisco J. Cazorla. 603-606 [doi]
- HW-SW integration for energy-efficient/variability-aware computingGasser Ayad, Andrea Acquaviva, Enrico Macii, Brahim Sahbi, Romain Lemaire. 607-611 [doi]
- Near-threshold voltage design in nanoscale CMOSVivek De. 612 [doi]
- Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETsEdith Beigné, Alexandre Valentian, Bastien Giraud, Olivier Thomas, T. Benoist, Yvain Thonnart, Serge Bernard, G. Moritz, O. Billoint, Y. Maneglia, Philippe Flatresse, Jean-Philippe Noel, Fady Abouzeid, Bertrand Pelloux-Prayer, A. Grover, Sylvain Clerc, Philippe Roche, Julien Le Coz, Sylvain Engels, Robin Wilson. 613-618 [doi]
- Carbon nanotube circuits: opportunities and challengesHai Wei, Max M. Shulaker, Gage Hills, Hong-Yu Chen, Chi-Shuen Lee, Luckshitha Liyanage, Jie Zhang, H.-S. Philip Wong, Subhasish Mitra. 619-624 [doi]
- Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICsPierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Shashikanth Bobba, Michele De Marchi, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli. 625-630 [doi]
- On-the-fly verification of memory consistency with concurrent relaxed scoreboardsLeandro S. Freitas, Eberle A. Rambo, Luiz C. V. dos Santos. 631-636 [doi]
- Fast cache simulation for host-compiled simulation of embedded softwareKun Lu, Daniel Mueller-Gritschneder, Ulf Schlichtmann. 637-642 [doi]
- A critical-section-level timing synchronization approach for deterministic multi-core instruction set simulationsFan-Wei Yu, Bo-Han Zeng, Yu-Hung Huang, Hsin-I. Wu, Che-Rung Lee, Ren-Song Tsay. 643-648 [doi]
- Multi-level phase analysis for sampling simulationJiaxin Li, Weihua Zhang, Haibo Chen, Binyu Zang. 649-654 [doi]
- Hypervised transient SPICE simulations of large netlists & workloads on multi-processor systemsGrigorios Lyras, Dimitrios Rodopoulos, Antonis Papanikolaou, Dimitrios Soudris. 655-658 [doi]
- A meta-model assisted coprocessor synthesis framework for compiler/architecture parameters customizationSotirios Xydis, Gianluca Palermo, Vittorio Zaccaria, Cristina Silvano. 659-664 [doi]
- Energy-efficient memory hierarchy for motion and disparity estimation in multiview video codingFelipe Sampaio, Bruno Zatt, Muhammad Shafique, Luciano Volcan Agostini, Sergio Bampi, Jörg Henkel. 665-670 [doi]
- Improving simulation speed and accuracy for many-core embedded platforms with ensemble modelsEdoardo Paone, N. Vahabi, Vittorio Zaccaria, Cristina Silvano, Diego Melpignano, Germain Haugou, Thierry Lepley. 671-676 [doi]
- Statically-scheduled application-specific processor design: a case-study on MMSE MIMO equalizationMostafa Rizk, Amer Baghdadi, Michel Jézéquel, Yasser Mohana, Youssef Atat. 677-680 [doi]
- Exploring resource mapping policies for dynamic clustering on NoC-based MPSoCsGustavo Girão, Thiago Santini, Flávio Rech Wagner. 681-684 [doi]
- Characterizing the performance benefits of fused CPU/GPU systems using FusionSimVitaly Zakharenko, Tor M. Aamodt, Andreas Moshovos. 685-688 [doi]
- Reliability-driven task mapping for lifetime extension of networks-on-chip based multiprocessor systemsAnup Das, Akash Kumar, Bharadwaj Veeravalli. 689-694 [doi]
- A work-stealing scheduling framework supporting fault toleranceYizhuo Wang, Weixing Ji, Feng Shi, Qi Zuo. 695-700 [doi]
- A cost-effective selective TMR for heterogeneous coarse-grained reconfigurable architectures based on DFG-level vulnerability analysisTakashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato. 701-706 [doi]
- CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processorsTuo Li 0001, Muhammad Shafique, Semeen Rehman, Swarnalatha Radhakrishnan, Roshan G. Ragel, Jude Angelo Ambrose, Jörg Henkel, Sri Parameswaran. 707-712 [doi]
- Reliability analysis for integrated circuit amplifiers used in neural measurement systemsNico Hellwege, Nils Heidmann, Dagmar Peters-Drolshagen, Steffen Paul. 713-716 [doi]
- On-line testing of permanent radiation effects in reconfigurable systemsLuca Cassano, Dario Cozzi, Sebastian Korf, Jens Hagemeyer, Mario Porrmann, Luca Sterpone. 717-720 [doi]
- An approach for redundancy in FlexRay networks using FPGA partial reconfigurationShanker Shreejith, Kizheppatt Vipin, Suhaib A. Fahmy, Martin Lukasiewycz. 721-724 [doi]
- Energy-efficient multicore chip design through cross-layer approachPaul Wettin, Jacob Murray, Partha Pratim Pande, Behrooz Shirazi, Amlan Ganguly. 725-730 [doi]
- Breaking the energy barrier in fault-tolerant caches for multicore systemsPaul Ampadu, Meilin Zhang, Vladimir Stojanovic. 731-736 [doi]
- Testing for SoCs with advanced static and dynamic power-management capabilitiesXrysovalantis Kavousianos, Krishnendu Chakrabarty. 737-742 [doi]
- Towards adaptive test of multi-core RF SoCsRajesh Mittal, Lakshmanan Balasubramanian, Y. B. Chethan Kumar, V. R. Devanathan, Mudasir Kawoosa, Rubin A. Parekhji. 743-748 [doi]
- A satisfiability approach to speed assignment for distributed real-time systemsPratyush Kumar, Devesh B. Chokshi, Lothar Thiele. 749-754 [doi]
- Data mining MPSoC simulation traces to identify concurrent memory access patternsSofiane Lagraa, Alexandre Termier, Frédéric Pétrot. 755-760 [doi]
- Model-based energy optimization of automotive control systemsJoost-Pieter Katoen, Thomas Noll, Hao Wu, Thomas Santen, Dirk Seifert. 761-766 [doi]
- Formal analysis of sporadic bursts in real-time systemsSophie Quinton, Mircea Negrean, Rolf Ernst. 767-772 [doi]
- Development of low power many-core SoC for multimedia applicationsTakashi Miyamori, Hui Xu, Takeshi Kodaka, Hiroyuki Usui, Toru Sano, Jun Tanabe. 773-777 [doi]
- SoC low-power practices for wireless applicationsNicolas Darbel, Stéphane Lecomte. 778 [doi]
- 3D integration for power-efficient computingDenis Dutoit, Eric Guthmuller, Ivan Miro Panades. 779-784 [doi]
- Verifying safety and liveness for the FlexTM hybrid transactional memoryParosh Aziz Abdulla, Sandhya Dwarkadas, Ahmed Rezine, Arrvindh Shriraman, Yunyun Zhu. 785-790 [doi]
- QF BV model checking with property directed reachabilityTobias Welp, Andreas Kuehlmann. 791-796 [doi]
- A semi-canonical form for sequential AIGsAlan Mishchenko, Niklas Eén, Robert K. Brayton, Michael L. Case, Pankaj Chauhan, Nikhil Sharma. 797-802 [doi]
- Fast cone-of-influence computation and estimation in problems with multiple propertiesC. Loiacono, M. Palena, P. Pasini, D. Patti, S. Quer, S. Ricossa, D. Vendraminetto, J. Baumgartner. 803-806 [doi]
- Using cubes of non-state variables with property directed reachabilityJohn D. Backes, Marc D. Riedel. 807-810 [doi]
- Bridging the gap between dual propagation and CNF-based QBF solvingAlexandra Goultiaeva, Martina Seidl, Armin Biere. 811-814 [doi]
- Dynamic configuration prefetching based on piecewise linear predictionAdrian Alin Lifa, Petru Eles, Zebo Peng. 815-820 [doi]
- An automatic tool flow for the combined implementation of multi-mode circuitsBrahim Al Farisi, Karel Bruneel, João M. P. Cardoso, Dirk Stroobandt. 821-826 [doi]
- Support for dynamic issue width in VLIW processors using generic binariesAnthony Brandon, Stephan Wong. 827-832 [doi]
- The RecoBlock SoC platform: a flexible array of reusable run-time-reconfigurable IP-blocksByron Navas, Ingo Sander, Johnny Öberg. 833-838 [doi]
- DANCE: distributed application-aware node configuration engine in shared reconfigurable sensor networksChih-Ming Hsieh, Zhonglei Wang, Jörg Henkel. 839-842 [doi]
- Hybrid interconnect design for heterogeneous hardware acceleratorsCuong Pham-Quoc, Jan Heisswolf, Stephan Werner, Zaid Al-Ars, Jürgen Becker, Koen Bertels. 843-846 [doi]
- OAP: an obstruction-aware cache management policy for STT-RAM last-level cachesJue Wang, Xiangyu Dong, Yuan Xie. 847-852 [doi]
- STT-RAM designs supporting dual-port accessesXiuyuan Bi, Mohamed Anis Weldon, Hai Li. 853-858 [doi]
- Low cost power failure protection for MLC NAND flash storage systems with PRAM/DRAM hybrid bufferJie Guo, Jun Yang 0002, Youtao Zhang, Yiran Chen. 859-864 [doi]
- SPaC: a segment-based parallel compression for backup acceleration in nonvolatile processorsXiao Sheng, Yiqun Wang, Yongpan Liu, Huazhong Yang. 865-868 [doi]
- The design of sustainable wireless sensor network node using solar energy and phase change memoryPing Zhou, Youtao Zhang, Jun Yang 0002. 869-872 [doi]
- Optical look up tableZhen Li, Sébastien Le Beux, Christelle Monat, Xavier Letartre, Ian O'Connor. 873-876 [doi]
- A verilog-a model for reconfigurable logic gates based on graphene pn-junctionsSandeep Miryala, Mehrdad Montazeri, Andrea Calimera, Enrico Macii, Massimo Poncino. 877-880 [doi]
- Optimal control of a grid-connected hybrid electrical energy storage system for homesYanzhi Wang, Xue Lin, Massoud Pedram, Sangyoung Park, Naehyuck Chang. 881-886 [doi]
- Radar signature in multiple target tracking system for driver assistant applicationHaisheng Liu, Smaïl Niar. 887-892 [doi]
- Development of a fully implantable recording system for ECoG signalsJonas Pistor, Janpeter Hoeffmann, David Rotermund, Elena Tolstosheeva, Tim Schellenberg, Dmitriy Boll, Victor Gordillo-Gonzalez, Sunita Mandon, Dagmar Peters-Drolshagen, Andreas K. Kreiter, Martin Schneider, Walter Lang, Klaus Pawelzik, Steffen Paul. 893-898 [doi]
- A methodology for embedded classification of heartbeats using random projectionsRuben Braojos, Giovanni Ansaloni, David Atienza. 899-904 [doi]
- A survey of multi-source energy harvesting systemsAlex S. Weddell, Michele Magno, Geoff V. Merrett, Davide Brunelli, Bashir M. Al-Hashimi, Luca Benini. 905-908 [doi]
- Capital cost-aware design and partial shading-aware architecture optimization of a reconfigurable photovoltaic systemYanzhi Wang, Xue Lin, Massoud Pedram, Jaemin Kim, Naehyuck Chang. 909-912 [doi]
- An ultra-low power hardware accelerator architecture for wearable computers using dynamic time warpingReza Lotfian, Roozbeh Jafari. 913-916 [doi]
- Efficient cache architectures for reliable hybrid voltage operation using EDC codesBojan Maric, Jaume Abella, Mateo Valero. 917-920 [doi]
- Efficient software-based fault tolerance approach on multicore platformsHamid Mushtaq, Zaid Al-Ars, Koen Bertels. 921-926 [doi]
- Using explicit output comparisons for fault tolerant scheduling (FTS) on modern high-performance processorsYue Gao, Sandeep K. Gupta, Melvin A. Breuer. 927-932 [doi]
- Low cost permanent fault detection using ultra-reduced instruction set co-processorsSundaram Ananthanarayanan, Siddharth Garg, Hiren D. Patel. 933-938 [doi]
- Improving fault tolerance utilizing hardware-software-co-synthesisHeinz Riener, Stefan Frehse, Görschwin Fey. 939-942 [doi]
- A dynamic self-adaptive correction method for error resilient applicationLuming Yan, Huaguo Liang, Zhengfeng Huang. 943-946 [doi]
- From embedded multi-core SoCs to scale-out processorsMarcello Coppola, Babak Falsafi, John Goodacre, George Kornaros. 947-951 [doi]
- UTBB FD-SOI: a process/design symbiosis for breakthrough energy-efficiencyPhilippe Magarshack, Philippe Flatresse, Giorgio Cesana. 952-957 [doi]
- Wireless interconnect for board and chip levelGerhard Fettweis, Najeeb ul Hassan, Lukas Landau, Erik Fischer. 958-963 [doi]
- Future memory and interconnect technologiesYuan Xie. 964-969 [doi]
- Optimized scheduling of multi-IMA partitions with exclusive region for synchronized real-time multi-core systemsJung-Eun Kim, Man-Ki Yoon, Sungjin Im, Richard M. Bradford, Lui Sha. 970-975 [doi]
- Quality-aware media scheduling on MPSoC platformsDeepak Gangadharan, Samarjit Chakraborty, Roger Zimmermann. 976-981 [doi]
- Priority assignment for event-triggered systems using mathematical programmingMartin Lukasiewycz, Sebastian Steinhorst, Samarjit Chakraborty. 982-987 [doi]
- Efficient and scalable OpenMP-based system-level designAlessandro Cilardo, Luca Gallo, Antonino Mazzeo, Nicola Mazzocca. 988-991 [doi]
- Utilizing voltage-frequency islands in C-to-RTL synthesis for streaming applicationsXinyu He, Shuangchen Li, Yongpan Liu, Xiaobo Sharon Hu, Huazhong Yang. 992-995 [doi]
- Minimization of P-circuits using Boolean relationsAnna Bernasconi, Valentina Ciriani, Gabriella Trucco, Tiziano Villa. 996-1001 [doi]
- Intuitive ECO synthesis for high performance circuitsHaoxing Ren, Ruchir Puri, Lakshmi N. Reddy, Smita Krishnaswamy, Cindy Washburn, Joel Earl, Joachim Keinert. 1002-1007 [doi]
- Retiming for Soft Error Minimization Under Error-Latching Window ConstraintsYinghai Lu, Hai Zhou. 1008-1013 [doi]
- Biconditional BDD: a novel canonical BDD for logic synthesis targeting XOR-rich circuitsLuca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli. 1014-1017 [doi]
- Optimizing BDDs for time-series dataset manipulationStergios Stergiou, Jawahar Jain. 1018-1021 [doi]
- Incorporating the impacts of workload-dependent runtime variations into timing analysisFarshad Firouzi, Saman Kiamehr, Mehdi Baradaran Tahoori, Sani Nassif. 1022-1025 [doi]
- Exploring topologies for source-synchronous ring-based network-on-chipAyan Mandal, Sunil P. Khatri, Rabi N. Mahapatra. 1026-1031 [doi]
- Proactive aging management in heterogeneous NoCs through a criticality-driven routing approachDean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy. 1032-1037 [doi]
- Sensor-wise methodology to face NBTI stress of NoC buffersDavide Zoni, William Fornaciari. 1038-1043 [doi]
- An area-efficient network interface for a TDM-based network-on-chipJens Sparsø, Evangelia Kasapaki, Martin Schoeberl. 1044-1047 [doi]
- CARS: congestion-aware request scheduler for network interfaces in NoC-based manycore systemsMasoud Daneshtalab, Masoumeh Ebrahimi, Juha Plosila, Hannu Tenhunen. 1048-1051 [doi]
- Designing tightly-coupled extension units for the STxP70 processorYves Janin, Valérie Bertin, Hervé Chauvet, Thomas Deruyter, Christophe Eichwald, Olivier-André Giraud, Vincent Lorquet, Thomas Thery. 1052-1053 [doi]
- A fast and accurate methodology for power estimation and reduction of programmable architecturesErwan Piriou, Raphaël David, Fahim Rahim, Solaiman Rahim. 1054-1055 [doi]
- A gate level methodology for efficient statistical leakage estimation in complex 32nm circuitsSmriti Joshi, Anne Lombardot, Marc Belleville, Edith Beigné, Stéphane Girard. 1056-1057 [doi]
- A near-future prediction method for low power consumption on a many-core processorTakeshi Kodaka, Akira Takeda, Shunsuke Sasaki, Akira Yokosawa, Toshiki Kizu, Takahiro Tokuyoshi, Hui Xu, Toru Sano, Hiroyuki Usui, Jun Tanabe, Takashi Miyamori, Nobu Matsumoto. 1058-1059 [doi]
- Time- and angle-triggered real-time kernelDamien Chabrol, Didier Roux, Vincent David, Mathieu Jan, Moha Ait Hmid, Patrice Oudin, Gilles Zeppa. 1060-1062 [doi]
- An extremely compact JPEG encoder for adaptive embedded systemsJosef Schneider, Sri Parameswaran. 1063-1064 [doi]
- Non-invasive pre-bond TSV test using ring oscillators and multiple voltage levelsSergej Deutsch, Krishnendu Chakrabarty. 1065-1070 [doi]
- LFSR seed computation and reduction using SMT-based fault-chainingDhrumeel Bakshi, Michael S. Hsiao. 1071-1076 [doi]
- Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detectionSébastien Sarrazin, Samuel Evain, Lirida Alves de Barros Naviner, Yannick Bonhomme, Valentin Gherman. 1077-1082 [doi]
- On candidate fault sets for fault diagnosis and dominance graphs of equivalence classesIrith Pomeranz. 1083-1088 [doi]
- A fast and Effective DFT for test and diagnosis of power switches in SoCsXiaoyu Huang, Jimson Mathew, Rishad A. Shafik, Subhasis Bhattacharjee, Dhiraj K. Pradhan. 1089-1092 [doi]
- Control-quality driven design of cyber-physical systems with robustness guaranteesAmir Aminifar, Petru Eles, Zebo Peng, Anton Cervin. 1093-1098 [doi]
- Compositional analysis of switched ethernet topologiesReinhard Schneider 0001, Licong Zhang, Dip Goswami, Alejandro Masrur, Samarjit Chakraborty. 1099-1104 [doi]
- Supervisor synthesis for controller upgradesJohannes Kloos, Rupak Majumdar. 1105-1110 [doi]
- Event density analysis for event triggered control systemsTobias Bund, Benjamin Menhorn, Frank Slomka. 1111-1116 [doi]
- Model predictive control over delay-based differentiated services control networksRiccardo Muradore, Davide Quaglia, Paolo Fiorini. 1117-1122 [doi]
- Multirate controller design for resource- and schedule-constrained automotive ECUsDip Goswami, Alejandro Masrur, Reinhard Schneider 0001, Chun Jason Xue, Samarjit Chakraborty. 1123-1126 [doi]
- Design of an ultra-low power device for aircraft structural health monitoringAlessandro Perelli, Carlo Caione, Luca De Marchi, Davide Brunelli, Alessandro Marzani, Luca Benini. 1127-1130 [doi]
- Qualification and testing process to implement anti-counterfeiting technologies into IC packagesNathalie Kae-Nune, Stephanie Pesseguier. 1131-1136 [doi]
- Anti-counterfeiting with hardware intrinsic securityVincent van der Leest, Pim Tuyls. 1137-1142 [doi]
- Sustainable energy policies: research challenges and opportunitiesMichela Milano. 1143-1148 [doi]
- Self-aware cyber-physical systems and applications in smart buildings and citiesLevent Gürgen, Ozan Gunalp, Yazid Benazzouz, Mathieu Gallissot. 1149-1154 [doi]
- Perpetual and low-cost power meter for monitoring residential and industrial appliancesDanilo Porcarelli, Domenico Balsamo, Davide Brunelli, Giacomo Paci. 1155-1160 [doi]
- Analytical timing estimation for temporally decoupled TLMs considering resource conflictsKun Lu, Daniel Mueller-Gritschneder, Ulf Schlichtmann. 1161-1166 [doi]
- Towards performance analysis of SDFGs mapped to shared-bus architectures using model-checkingMaher Fakih, Kim Grüttner, Martin Fränzle, Achim Rettberg. 1167-1172 [doi]
- Toward polychronous analysis and validation for timed software architectures in AADLYue Ma, Huafeng Yu, Thierry Gautier, Paul Le Guernic, Jean-Pierre Talpin, Loïc Besnard, Maurice Heitz. 1173-1178 [doi]
- Tuning dynamic data flow analysis to support design understandingJan Malburg, Alexander Finder, Görschwin Fey. 1179-1184 [doi]
- Fast and accurate TLM simulations using temporal decoupling for FIFO-based communicationsClaude Helmstetter, Jérôme Cornet, Bruno Galilée, Matthieu Moy, Pascal Vivet. 1185-1188 [doi]
- Determining relevant model elements for the verification of UML/OCL specificationsJulia Seiter, Robert Wille, Mathias Soeken, Rolf Drechsler. 1189-1192 [doi]
- Towards a generic verification methodology for system modelsRobert Wille, Martin Gogolla, Mathias Soeken, Mirco Kuhlmann, Rolf Drechsler. 1193-1196 [doi]
- m CMOS for energy harvestersBiswajit Mishra, Cyril Botteron, Gabriele Tasselli, Chritian Robert, Pierre-André Farine. 1197-1202 [doi]
- Saliency aware display power managementYang Xiao, Kevin M. Irick, Vijaykrishnan Narayanan, Donghwa Shin, Naehyuck Chang. 1203-1208 [doi]
- Active-mode leakage reduction with data-retained power gatingAndrew B. Kahng, Seokhyeong Kang, Bongil Park. 1209-1214 [doi]
- A power-driven thermal sensor placement algorithm for dynamic thermal managementHai Wang, Sheldon X.-D. Tan, Sahana Swarup, Xuexin Liu. 1215-1220 [doi]
- Active power-gating-induced power/ground noise alleviation using parasitic capacitance of on-chip memoriesXuan Wang, Jiang Xu, Wei Zhang 0012, Xiaowen Wu, Yaoyao Ye, Zhehui Wang, Mahdi Nikdast, Zhe Wang. 1221-1224 [doi]
- Adaptive thermal management for portable system batteries by forced convection coolingQing Xie, Siyu Yue, Massoud Pedram, Donghwa Shin, Naehyuck Chang. 1225-1228 [doi]
- Sparse-rotary oscillator array (SROA) design for power and skew reductionYing Teng, Baris Taskin. 1229-1234 [doi]
- m-output lookup tablesAlireza Shafaei, Mehdi Saeedi, Massoud Pedram. 1235-1240 [doi]
- 3D-MMC: a modular 3D multi-core architecture with efficient resource poolingTiansheng Zhang, Alessandro Cevrero, Giulia Beanato, Panagiotis Athanasopoulos, Ayse Kivilcim Coskun, Yusuf Leblebici. 1241-1246 [doi]
- Cache coherence enabled adaptive refresh for volatile STT-RAMJianhua Li, Liang Shi, Qing'an Li, Chun Jason Xue, Yiran Chen, Yinlong Xu. 1247-1250 [doi]
- Is TSV-based 3D integration suitable for inter-die memory repair?Mihai Lefter, George Razvan Voicu, Mottaqiallah Taouil, Marius Enachescu, Said Hamdioui, Sorin Dan Cotofana. 1251-1254 [doi]
- Thermomechanical stress-aware management for 3D IC designsQiaosha Zou, Tao Zhang, Eren Kursun, Yuan Xie. 1255-1258 [doi]
- Is split manufacturing secure?Jeyavijayan Rajendran, Ozgur Sinanoglu, Ramesh Karri. 1259-1264 [doi]
- Trojan detection via delay measurements: a new approach to select paths and vectors to maximize effectiveness and minimize costByeongju Cha, Sandeep K. Gupta. 1265-1270 [doi]
- High-sensitivity hardware trojan detection using multimodal characterizationKangqiao Hu, Abdullah Nazma Nowroz, Sherief Reda, Farinaz Koushanfar. 1271-1276 [doi]
- Reverse engineering digital circuits using functional analysisPramod Subramanyan, Nestan Tsiskaridze, Kanika Pasricha, Dillon Reisman, Adriana Susnea, Sharad Malik. 1277-1280 [doi]
- A practical testing framework for isolating hardware timing channelsJason Oberg, Sarah Meiklejohn, Timothy Sherwood, Ryan Kastner. 1281-1284 [doi]
- Threshold voltage distribution in MLC NAND flash memory: characterization, analysis, and modelingYu Cai, Erich F. Haratsch, Onur Mutlu, Ken Mai. 1285-1290 [doi]
- Efficient importance sampling for high-sigma yield analysis with adaptive online surrogate modelingJian Yao, Zuochang Ye, Yan Wang. 1291-1296 [doi]
- Metastability challenges for 65nm and beyond: simulation and measurementsSalomon Beer, Ran Ginosar, Jerome Cox, Tom Chaney, David M. Zar. 1297-1302 [doi]
- Design and implementation of an adaptive proactive reconfiguration technique for SRAM cachesPeyman Pouyan, Esteve Amat, Francesc Moll, Antonio Rubio. 1303-1306 [doi]
- Architecture and optimal configuration of a real-time multi-channel memory controllerManil Dev Gomony, Benny Akesson, Kees Goossens. 1307-1312 [doi]
- Holistic design parameter optimization of multiple periodic resources in hierarchical schedulingMan-Ki Yoon, Jung-Eun Kim, Richard M. Bradford, Lui Sha. 1313-1318 [doi]
- Robust and extensible task implementations of synchronous finite state machinesQi Zhu, Peng Deng, Marco Di Natale, Haibo Zeng. 1319-1324 [doi]
- FBLT: a real-time contention manager with improved schedulabilityMohammed El-Shambakey, Binoy Ravindran. 1325-1330 [doi]
- A virtual prototyping platform for real-time systems with a case study for a two-wheeled robotDaniel Mueller-Gritschneder, Kun Lu, Erik Wallander, Marc Greim, Ulf Schlichtmann. 1331-1334 [doi]
- Sufficient real-time analysis for an engine control unit with constant angular velocitiesVictor Pollex, Timo Feld, Frank Slomka, Ulrich Margull, Ralph Mader, Gerhard Wirrer. 1335-1338 [doi]
- Roadmap towards ultimately-efficient zeta-scale datacentersPatrick Ruch, Thomas Brunschwiler, Stephan Paredes, Gerhard Ingmar Meijer, Bruno Michel. 1339-1344 [doi]
- Correlation-aware virtual machine allocation for energy-efficient datacentersJungsoo Kim, Martino Ruggiero, David Atienza, Marcel Lederberger. 1345-1350 [doi]
- Resource efficient computing for warehouse-scale datacentersChristos Kozyrakis. 1351-1356 [doi]
- On the use of GP-GPUs for accelerating compute-intensive EDA applicationsValeria Bertacco, Debapriya Chatterjee, Nicola Bombieri, Franco Fummi, Sara Vinco, A. M. Kaushik, Hiren D. Patel. 1357-1366 [doi]
- Substitute-and-simplify: a unified design paradigm for approximate and quality configurable circuitsSwagath Venkataramani, Kaushik Roy, Anand Raghunathan. 1367-1372 [doi]
- Enhancing multicore reliability through wear compensation in online assignment and schedulingThidapat Chantem, Xiang Yun, Xiaobo Sharon Hu, Robert P. Dick. 1373-1378 [doi]
- NUMANA: a hybrid <u>num</u>erical and <u>ana</u>lytical thermal simulator for 3-D ICsYu-Min Lee, Tsung-Heng Wu, Pei-Yu Huang, Chi-Ping Yang. 1379-1384 [doi]
- Explicit transient thermal simulation of liquid-cooled 3D ICsAlain Fourmigue, Giovanni Beltrame, Gabriela Nicolescu. 1385-1390 [doi]
- Mitigating dark-silicon problems using superlattice-based thermoelectric coolersFrancesco Paterna, Sherief Reda. 1391-1394 [doi]
- Run-time probabilistic detection of miscalibrated thermal sensors in many-core systemsJia Zhao, Shiting (Justin) Lu, Wayne Burleson, Russell Tessier. 1395-1398 [doi]
- GLA: gate-level abstraction revisitedAlan Mishchenko, Niklas Eén, Robert K. Brayton, Jason Baumgartner, Hari Mony, Pradeep Kumar Nalla. 1399-1404 [doi]
- Lemma localization: a practical method for downsizing SMT-interpolantsFlorian Pigorsch, Christoph Scholl. 1405-1410 [doi]
- Core minimization in SAT-based abstractionAnton Belov, Huan Chen 0001, Alan Mishchenko, Joao Marques-Silva. 1411-1416 [doi]
- Optimization techniques for craig interpolant compaction in unbounded model checkingGianpiero Cabodi, C. Loiacono, D. Vendraminetto. 1417-1422 [doi]
- Formal analysis of steady state errors in feedback control systems using HOL-lightOsman Hasan, Muhammad Ahmad. 1423-1426 [doi]
- A novel concurrent cache-friendly binary decision diagram construction for multi-core platformsMahmoud Elbayoumi, Michael S. Hsiao, Mustafa Y. ElNainay. 1427-1430 [doi]
- A low-power and low-voltage BBPLL-based sensor interface in 130nm CMOS for wireless sensor networksJelle Van Rethy, Hans Danneels, Valentijn De Smedt, Wim Dehaene, Georges G. E. Gielen. 1431-1435 [doi]
- Reachability analysis of nonlinear analog circuits through iterative reachable set reductionSeyed Nematollah Ahmadyan, Shobha Vasudevan. 1436-1441 [doi]
- Formal verification of analog circuit parameters across variation utilizing SATMerritt Miller, Forrest Brewer. 1442-1447 [doi]
- Extracting analytical nonlinear models from analog circuits by recursive vector fitting of transfer function trajectoriesDimitri de Jonghe, Dirk Deschrijver, Tom Dhaene, Georges G. E. Gielen. 1448-1453 [doi]
- Statistical modeling with the virtual source MOSFET modelLi Yu, Lan Wei, Dimitri A. Antoniadis, Ibrahim M. Elfadel, Duane S. Boning. 1454-1457 [doi]
- Automatic circuit sizing technique for the analog circuits with flexible TFTs considering process variation and bending effectsYen-Lung Chen, Wan-Rong Wu, Guan-Ruei Lu, Chien-Nan Jimmy Liu. 1458-1461 [doi]
- On-line functionally untestable fault identification in embedded processor coresPaolo Bernardi, Michele Bonazza, Ernesto Sánchez, Matteo Sonza Reorda, Oscar Ballan. 1462-1467 [doi]
- Capturing vulnerability variations for register filesJavier Carretero, Enric Herrero, Matteo Monchiero, Tanausú Ramírez, Xavier Vera. 1468-1473 [doi]
- Error detection in ternary CAMs using bloom filtersSalvatore Pontarelli, Marco Ottavi, Adrian Evans, Shi-Jie Wen. 1474-1479 [doi]
- AVF-driven parity optimization for MBU protection of in-core memory arraysMichail Maniatakos, Maria K. Michael, Yiorgos Makris. 1480-1485 [doi]
- An enhanced double-TSV scheme for defect tolerance in 3D-ICHsiu-Chuan Shih, Cheng-Wen Wu. 1486-1489 [doi]
- Mempack: an order of magnitude reduction in the cost, risk, and time for memory compiler certificationKartik Mohanram, Matthew Wartell, Sundar Iyer. 1490-1493 [doi]
- Exploiting replicated checkpoints for soft error detection and correctionFahrettin Koc, Kenan Bozdas, Burak Karsli, Oguz Ergin. 1494-1497 [doi]
- Game-theoretic analysis of decentralized core allocation schemes on many-core systemsStefan Wildermann, Tobias Ziermann, Jürgen Teich. 1498-1503 [doi]
- Enabling fine-grained OpenMP tasking on tightly-coupled shared memory clustersPaolo Burgio, Giuseppe Tagliavini, Andrea Marongiu, Luca Benini. 1504-1509 [doi]
- ARTM: a lightweight fork-join framework for many-core embedded systemsMaroun Ojail, Raphaël David, Yves Lhuillier, Alexandre Guerre. 1510-1515 [doi]
- Pipelets: self-organizing software pipelines for many-core architecturesJanmartin Jahn, Jörg Henkel. 1516-1521 [doi]
- An integrated approach for managing the lifetime of flash-based SSDsSungjin Lee, Taejin Kim, Jisung Park, Jihong Kim. 1522-1525 [doi]
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- Dr. Frankenstein's dream made possible: implanted electronic devicesDaniela De Venuto, Alberto L. Sangiovanni-Vincentelli. 1531-1536 [doi]
- Addressing the healthcare cost dilemma by managing health instead of managing illness: an opportunity for wearable wireless sensorsChris Van Hoof, Julien Penders. 1537-1539 [doi]
- Electronic implants: power delivery and managementJacopo Olivo, Sara S. Ghoreishizadeh, Sandro Carrara, Giovanni De Micheli. 1540-1545 [doi]
- Cyborg insects, neural interfaces and other things: building interfaces between the synthetic and the multicellularJ. Van Kleef, T. Massey, P. Ledochowitsch, R. Muller, R. Tiefenauer, T. Blanche, Hirotaka Sato, M. M. Maharbiz. 1546 [doi]
- Share with care: a quantitative evaluation of sharing approaches in high-level synthesisAlex Kondratyev, Luciano Lavagno, Mike Meyer, Yosinori Watanabe. 1547-1552 [doi]
- FPGA latency optimization using system-level transformations and DFG restructuringDaniel Gomez-Prado, Maciej J. Ciesielski, Russell Tessier. 1553-1558 [doi]
- A transparent and energy aware reconfigurable multiprocessor platform for simultaneous ILP and TLP exploitationMateus B. Rutzig, Antonio Carlos Schneider Beck, Luigi Carro. 1559-1564 [doi]
- High-level modeling and synthesis for embedded FPGAsXiaolin Chen, Shuai Li, Jochen Schleifer, Thomas Coenen, Anupam Chattopadhyay, Gerd Ascheid, Tobias G. Noll. 1565-1570 [doi]
- Scheduling independent liveness analysis for register binding in high level synthesisVito Giovanni Castellana, Fabrizio Ferrandi. 1571-1574 [doi]
- Fast shared on-chip memory architecture for efficient hybrid computing with CGRAsJongeun Lee, Yeonghun Jeong, Sungsok Seo. 1575-1578 [doi]
- Compiling control-intensive loops for CGRAs with state-based full predicationKyuseung Han, Kiyoung Choi, Jongeun Lee. 1579-1582 [doi]
- DeBAR: deflection based adaptive router with minimal bufferingJohn Jose, Bhawna Nayak, Kranthi Kumar, Madhu Mutyam. 1583-1588 [doi]
- Contrasting wavelength-routed optical NoC topologies for power-efficient 3D-stacked multicore processors using physical-layer analysisLuca Ramini, Paolo Grani, Sandro Bartolini, Davide Bertozzi. 1589-1594 [doi]
- Topology-agnostic fault-tolerant NoC routing methodEduardo Wächter, Augusto Erichsen, Alexandre M. Amory, Fernando Moraes. 1595-1600 [doi]
- Fault-tolerant routing algorithm for 3D NoC using Hamiltonian path strategyMasoumeh Ebrahimi, Masoud Daneshtalab, Juha Plosila. 1601-1604 [doi]
- Modeling and analysis of fault-tolerant distributed memories for networks-on-chipAbbas BanaiyanMofrad, Nikil Dutt, Gustavo Girão. 1605-1608 [doi]
- System-level modeling of energy in TLM for early validation of power and thermal managementTayeb Bouhadiba, Matthieu Moy, Florence Maraninchi. 1609-1614 [doi]
- System-level modeling and microprocessor reliability analysis for backend wearout mechanismsChang-Chih Chen, Linda Milor. 1615-1620 [doi]
- Automatic success tree-based reliability analysis for the consideration of transient and permanent faultsHananeh Aliee, Michael Glaß, Felix Reimann, Jürgen Teich. 1621-1626 [doi]
- Hybrid prototyping of multicore embedded systemsEhsan Saboori, Samar Abdi. 1627-1630 [doi]
- Communication and migration energy aware design space exploration for multicore systems with intermittent faultsAnup Das, Akash Kumar, Bharadwaj Veeravalli. 1631-1636 [doi]
- 40.4fJ/bit/mm low-swing on-chip signaling with self-resetting logic repeaters embedded within a mesh NoC in 45nm SOI CMOSSunghyun Park, Masood Qazi, Li-Shiuan Peh, Anantha P. Chandrakasan. 1637-1642 [doi]
- 3D reconfigurable power switch network for demand-supply matching between multi-output power converters and many-core microprocessorsKanwen Wang, Hao Yu, Benfei Wang, Chun Zhang. 1643-1648 [doi]
- Thermal-aware datapath merging for coarse-grained reconfigurable processorsSotirios Xydis, Gianluca Palermo, Cristina Silvano. 1649-1654 [doi]
- Placement optimization of power supply pads based on localityPingqiang Zhou, Vivek Mishra, Sachin S. Sapatnekar. 1655-1660 [doi]
- GPU-friendly floating random walk algorithm for capacitance extraction of VLSI interconnectsKuangya Zhai, Wenjian Yu, Hao Zhuang. 1661-1666 [doi]
- Periodic jitter and bounded uncorrelated jitter decomposition using incoherent undersamplingNicholas Tzou, Debesh Bhatta, Sen-Wen Hsiao, Abhijit Chatterjee. 1667-1672 [doi]
- Crosstalk avoidance codes for 3D VLSIRajeev Kumar, Sunil P. Khatri. 1673-1678 [doi]
- Large-scale flip-chip power grid reduction with geometric templatesZhuo Feng. 1679-1682 [doi]
- Impact of adaptive voltage scaling on aging-aware signoffTuck Boon Chan, Wei-Ting Jonas Chan, Andrew B. Kahng. 1683-1688 [doi]
- A parallel fast transform-based preconditioning approach for electrical-thermal co-simulation of power delivery networksKonstantis Daloukas, Alexia Marnari, Nestor E. Evmorfopoulos, Panagiota Tsompanopoulou, George I. Stamoulis. 1689-1694 [doi]
- Hierarchically focused guardbanding: an adaptive approach to mitigate PVT variations and agingAbbas Rahimi, Luca Benini, Rajesh K. Gupta. 1695-1700 [doi]
- Effective power network prototyping via statistical-based clustering and sequential linear programmingShih-Ying Sean Liu, Chieh-Jui Lee, Chuan-Chia Huang, Hung-Ming Chen, Chang-Tzu Lin, Chia-Hsin Lee. 1701-1706 [doi]
- A network-flow based algorithm for power density mitigation at post-placement stageShih-Ying Sean Liu, Ren-Guo Luo, Hung-Ming Chen. 1707-1710 [doi]
- An efficient wirelength model for analytical placementB. N. B. Ray, Shankar Balachandran. 1711-1714 [doi]
- Advances in asynchronous logic: from principles to GALS & NoC, recent industry applications, and commercial CAD toolsAlex Yakovlev, Pascal Vivet, Marc Renaudin. 1715-1724 [doi]
- Interactions of large scale EV mobility and virtual power plantsRandolf Mock, Tullio Salmon Cinotti, Johannes Reinschke, Luciano Bononi. 1725-1729 [doi]
- Innovative energy storage solutions for future electromobility in smart citiesKevin Green, Salvador Rodríguez González, Ruud Wijtvliet. 1730-1734 [doi]
- Automotive ethernet: in-vehicle networking and smart mobilityPeter Hank, Steffen Müller, Ovidiu Vermesan, Jeroen Van den Keybus. 1735-1739 [doi]
- Smart, connected and mobile: architecting future electric mobility ecosystemsOvidiu Vermesan, Lars-Cyril Julin Blystad, Reiner John, Peter Hank, Roy Bahr, Alessandro Moscatelli. 1740-1744 [doi]
- e-Mobility the next frontier for automotive industryRoberto Zafalon, Giovanni Coppola, Ovidiu Vermesan. 1745-1748 [doi]
- Semiconductor technologies for smart mobility managementReiner John, Martin Schulz, Ovidiu Vermesan, Kai Kriegel. 1749-1752 [doi]
- A new paradigm for trading off yield, area and performance to enhance performance per waferYue Gao, Melvin A. Breuer, Yanzhi Wang. 1753-1758 [doi]
- Leveraging variable function resilience for selective software reliability on unreliable hardwareSemeen Rehman, Muhammad Shafique, Pau Vilimelis Aceituno, Florian Kriebel, Jian-Jia Chen, Jörg Henkel. 1759-1764 [doi]
- Optimization of secure embedded systems with dynamic task setsKe Jiang, Petru Eles, Zebo Peng. 1765-1770 [doi]
- Shared memory aware MPSoC software deploymentTimo Schönwald, Alexander Viehl, Oliver Bringmann, Wolfgang Rosenstiel. 1771-1776 [doi]
- Fast and optimized task allocation method for low vertical link density 3-dimensional networks-on-chip based many core systemsHaoyuan Ying, Thomas Hollstein, Klaus Hofmann. 1777-1782 [doi]
- A spectral clustering approach to application-specific network-on-chip synthesisVladimir Todorov, Daniel Mueller-Gritschneder, Helmut Reinig, Ulf Schlichtmann. 1783-1788 [doi]
- A SPICE-compatible model of graphene nano-ribbon field-effect transistors enabling circuit-level delay and power analysis under process variationYing-Yu Chen, Artem Rogachev, Amit Sangai, Giuseppe Iannaccone, Gianluca Fiori, Deming Chen. 1789-1794 [doi]
- Systematic design of nanomagnet logic circuitsIndranil Palit, Xiaobo Sharon Hu, Joseph Nahas, Michael T. Niemier. 1795-1800 [doi]
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- D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memoryHiroki Noguchi, Kumiko Nomura, Keiko Abe, Shinobu Fujita, Eishi Arima, Kyundong Kim, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura. 1813-1818 [doi]
- MINJames Boley, Vikas Chandra, Robert C. Aitken, Benton H. Calhoun. 1819-1824 [doi]
- DWM-TAPESTRI - an energy efficient all-spin cache using domain wall shift based writesRangharajan Venkatesan, Mrigank Sharad, Kaushik Roy, Anand Raghunathan. 1825-1830 [doi]
- Co-synthesis of data paths and clock control paths for minimum-period clock gatingWen-Pin Tu, Shih-Hsu Huang, Chun-Hua Cheng. 1831-1836 [doi]
- Slack budgeting and slack to length converting for multi-bit flip-flop mergingChia-Chieh Lu, Rung-Bin Lin. 1837-1842 [doi]
- Area optimization on fixed analog floorplans using convex area functionsAhmet Unutulmaz, Günhan Dündar, Francisco V. Fernández. 1843-1848 [doi]
- PAGE: parallel agile genetic exploration towards utmost performance for analog circuit designPo-Cheng Pan, Hung-Ming Chen, Chien-Chih Lin. 1849-1854 [doi]
- Fast and efficient lagrangian relaxation-based discrete gate sizingVincius S. Livramento, Chrystian Guth, José Luís Güntzel, Marcelo O. Johann. 1855-1860 [doi]
- Enhanced metamodeling techniques for high-dimensional IC design estimation problemsAndrew B. Kahng, Bill Lin, Siddhartha Nath. 1861-1866 [doi]
- Sub-quadratic objectives in quadratic placementMarkus Struzyna. 1867-1872 [doi]
- CATALYST: planning layer directives for effective design closureYaoguang Wei, Zhuo Li, Cliff C. N. Sze, Shiyan Hu, Charles J. Alpert, Sachin S. Sapatnekar. 1873-1878 [doi]
- Closed-loop control for power and thermal management in multi-core processors: formal methods and industrial practiceIbrahim M. Elfadel, Radu Marculescu, David Atienza. 1879-1881 [doi]