Alexandru Plesco - researchr alias

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Viewing Publication 1 - 8 from 8

2021

Data-aware process networksChristophe Alias, Alexandru Plesco. CC 2021: 1-11 [doi]

2017

Optimizing Affine Control With Semantic FactorizationsChristophe Alias, Alexandru Plesco. taco, 14(4), 2017. [doi]

2013

Optimizing remote accesses for offloaded kernels: application to high-level synthesis for FPGAChristophe Alias, Alain Darte, Alexandru Plesco. date 2013: 575-580 [doi]

2012

Optimizing remote accesses for offloaded kernels: application to high-level synthesis for FPGAChristophe Alias, Alain Darte, Alexandru Plesco. ppopp 2012: 285-286 [doi]

FPGA-specific synthesis of loop-nests with pipelined computational coresChristophe Alias, Bogdan Pasca, Alexandru Plesco. mam, 36(8):606-619, 2012. [doi]

2011

Automatic Generation of FPGA-Specific Pipelined AcceleratorsChristophe Alias, Bogdan Pasca, Alexandru Plesco. arc 2011: 53-66 [doi]

An FPGA architecture for solving the Table Maker's DilemmaFlorent de Dinechin, Jean-Michel Muller, Bogdan Pasca, Alexandru Plesco. asap 2011: 187-194 [doi]

2010

Program Transformations and Memory Architecture Optimizations for High-Level Synthesis of Hardware Accelerators. (Transformations de programmes et optimisations de l'architecture mémoire pour la synthèse de haut niveau d'accélérateurs matériels)Alexandru Plesco. PhD thesis, École normale supérieure de Lyon, France, 2010. [doi]

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