Abstract is missing.
- Reconfigurable Computing for High Performance Networking ApplicationsGordon J. Brebner. 1 [doi]
- Biologically-Inspired Massively-Parallel Architectures: A Reconfigurable Neural Modelling PlatformSteve Furber. 2 [doi]
- A Reconfigurable Audio Beamforming Multi-Core ProcessorDimitris Theodoropoulos, Georgi Kuzmanov, Georgi Gaydadjiev. 3-15 [doi]
- A Regular Expression Matching Circuit Based on a Decomposed AutomatonHiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura. 16-28 [doi]
- Design and Implementation of a Multi-Core Crypto-Processor for Software Defined RadiosMichael Grand, Lilian Bossuet, Bertrand Le Gal, Guy Gogniat, Dominique Dallet. 29-40 [doi]
- Application Specific Memory Access, Reuse and Reordering for SDRAMSamuel Bayliss, George A. Constantinides. 41-52 [doi]
- Automatic Generation of FPGA-Specific Pipelined AcceleratorsChristophe Alias, Bogdan Pasca, Alexandru Plesco. 53-66 [doi]
- HLS Tools for FPGA: Faster Development with Better PerformanceAlexandre Cornu, Steven Derrien, Dominique Lavenier. 67-78 [doi]
- A (Fault-Tolerant):::2::: Scheduler for Real-Time HW TasksXabier Iturbe, Khaled Benkrid, Tughrul Arslan, Mikel Azkarate-askasua, Imanol Martinez. 79-87 [doi]
- A Compact Gaussian Random Number Generator for Small Word LengthsSubhasis Das, Sachin Patkar. 88-93 [doi]
- Accurate Floating Point Arithmetic through Hardware Error-Free TransformationsManouk V. Manoukian, George A. Constantinides. 94-101 [doi]
- Active Storage Networks for Accelerating K-Means Data ClusteringJanardhan Singaraju, John A. Chandy. 102-109 [doi]
- An FPGA Implementation for Texture Analysis Considering the Real-Time Requirements of Vision-Based SystemsMario Alberto Ibarra-Manzano, Dora Luz Almanza-Ojeda. 110-117 [doi]
- CReAMS: An Embedded Multiprocessor PlatformMateus B. Rutzig, Antonio Carlos Schneider Beck, Luigi Carro. 118-124 [doi]
- Dataflow Graph Partitioning for Optimal Spatio-Temporal Computation on a Coarse Grain Reconfigurable ArchitectureRatna Krishnamoorthy, Keshavan Varadarajan, Masahiro Fujita, Mythri Alle, S. K. Nandy, Ranjani Narayan. 125-132 [doi]
- A Pipeline Interleaved Heterogeneous SIMD Soft Processor Array Architecture for MIMO-OFDM DetectionXuezheng Chu, John McAllister, Roger Woods. 133-144 [doi]
- Design, Implementation, and Verification of an Adaptable Processor in Lava HDLStefan Schulze, Sergei Sawitzki. 145-156 [doi]
- Towards an Adaptable Multiple-ISA Reconfigurable ProcessorJair Fajardo Junior, Mateus B. Rutzig, Antonio Carlos Schneider Beck, Luigi Carro. 157-168 [doi]
- FPGA-Based Cherenkov Ring Recognition in Nuclear and Particle Physics ExperimentsMing Liu, Zhonghai Lu, Wolfgang Kuehn, Axel Jantsch. 169-180 [doi]
- FPGA-Based Smith-Waterman Algorithm: Analysis and Novel DesignYoshiki Yamaguchi, Kuen Hung Tsoi, Wayne Luk. 181-192 [doi]
- Index to Constant Weight Codeword ConverterJon T. Butler, Tsutomu Sasao. 193-205 [doi]
- On-Chip Ego-Motion Estimation Based on Optical FlowMauricio Vanegas, Leonardo Rubio, Matteo Tomasi, Javier Díaz, Eduardo Ros. 206-217 [doi]
- Comparison between Heterogeneous Mesh-Based and Tree-Based Application Specific FPGAUmer Farooq, Husain Parvez, Zied Marrakchi, Habib Mehrez. 218-229 [doi]
- Dynamic V::DD:: Switching Technique and Mapping Optimization in Dynamically Reconfigurable Processor for Efficient Energy ReductionTatsuya Yamamoto, Kazuei Hironaka, Yuki Hayakawa, Masayuki Kimura, Hideharu Amano, Kimiyoshi Usami. 230-241 [doi]
- MEMS Interleaving Read Operation of a Holographic Memory for Optically Reconfigurable Gate ArraysHironobu Morita, Minoru Watanabe. 242-252 [doi]
- FaRM: Fast Reconfiguration Manager for Reducing Reconfiguration Time Overhead on FPGAFrançois Duhem, Fabrice Muller, Philippe Lorenzini. 253-260 [doi]
- Feasibility Analysis of Reconfigurable Computing in Low-Power Wireless Sensor ApplicationsAndreas Engel, Björn Liebig, Andreas Koch. 261-268 [doi]
- Hierarchical Optical Flow Estimation Architecture Using Color CuesFrancisco Barranco, Matteo Tomasi, Javier Díaz, Eduardo Ros. 269-274 [doi]
- Magnetic Look-Up Table (MLUT) Featuring Radiation Hardness, High Performance and Low PowerYahya Lakys, Weisheng Zhao, Jacques-Olivier Klein, Claude Chappert. 275-280 [doi]
- Reconfigurable Stream-Processing Architecture for Sparse Linear SolversKevin Cunningham, Prawat Nagvajara. 281-286 [doi]
- The Krawczyk Algorithm: Rigorous Bounds for Linear Equation Solution on an FPGAChristophe Le Lann, David Boland, George A. Constantinides. 287-295 [doi]
- FPGA Accelerated Parallel Sparse Matrix Factorization for Circuit SimulationsWei Wu, Yi Shan, Xiaoming Chen, Yu Wang, Huazhong Yang. 302-315 [doi]
- FPGA Optimizations for a Pipelined Floating-Point Exponential UnitNikolaos Alachiotis, Alexandros Stamatakis. 316-327 [doi]
- NetStage/DPR: A Self-adaptable FPGA Platform for Application-Level Network SecuritySascha Mühlbach, Andreas Koch. 328-339 [doi]
- A Correlation Power Analysis Attack against Tate Pairing on FPGAWeibo Pan, William P. Marnane. 340-349 [doi]
- From Plasma to BeeFarm: Design Experience of an FPGA-Based Multicore PrototypeNehir Sönmez, Oriol Arcas, Gokhan Sayilar, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Satnam Singh, Mateo Valero. 350-362 [doi]
- Architectural Support for Multithreading on Reconfigurable HardwarePavel G. Zaykov, Georgi Kuzmanov. 363-374 [doi]
- High Performance Programmable FPGA Overlay for Digital Signal ProcessingSéamas McGettrick, Kunjan Patel, Chris J. Bleakley. 375-384 [doi]
- Secure Virtualization within a Multi-processor Soft-Core System-on-Chip ArchitectureAlexander Biedermann, Marc Stöttinger, Lijing Chen, Sorin A. Huss. 385-396 [doi]