Chang-Chih Chen - researchr alias

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Viewing Publication 1 - 22 from 22

2022

Optimal decision of dynamic wealth allocation with life insurance for mitigating health risk under market incompletenessChang-Chih Chen, Chia-Chien Chang, Edward W. Sun, Min-Teh Yu. eor, 300(2):727-742, 2022. [doi]

2020

SRAM Stability Analysis and Performance-Reliability Tradeoff for Different Cache ConfigurationsRui Zhang, Taizhi Liu, Kexin Yang, Chang-Chih Chen, Linda Milor. tvlsi, 28(3):620-633, 2020. [doi]

2018

Comprehensive Reliability-Aware Statistical Timing Analysis Using a Unified Gate-Delay Model for MicroprocessorsTaizhi Liu, Chang-Chih Chen, Linda Milor. tetc, 6(2):219-232, 2018. [doi]

2016

2015

Microprocessor Aging Analysis and Reliability Modeling Due to Back-End Wearout MechanismsChang-Chih Chen, Linda S. Milor. tvlsi, 23(10):2065-2076, 2015. [doi]

Processor-level reliability simulator for time-dependent gate dielectric breakdownChang-Chih Chen, Taizhi Liu, Soonyoung Cha, Linda S. Milor. mam, 39(8):950-960, 2015. [doi]

MBIST and statistical hypothesis test for time dependent dielectric breakdowns due to GOBD vs. BTDDB in an SRAM arrayWoongrae Kim, Chang-Chih Chen, Soonyoung Cha, Linda Milor. vts 2015: 1-6 [doi]

Estimation of remaining life using embedded SRAM for wearout parameter extractionWoongrae Kim, Chang-Chih Chen, Taizhi Liu, Soonyoung Cha, Linda Milor. iwasi 2015: 243-248 [doi]

Accurate standard cell characterization and statistical timing analysis using multivariate adaptive regression splinesTaizhi Liu, Chang-Chih Chen, Linda S. Milor. isqed 2015: 272-279 [doi]

System-level variation-aware aging simulator using a unified novel gate-delay model for bias temperature instability, hot carrier injection, and gate oxide breakdownTaizhi Liu, Chang-Chih Chen, Soonyoung Cha, Linda Milor. mr, 55(9-10):1334-1340, 2015. [doi]

Comprehensive reliability and aging analysis on SRAMs within microprocessor systemsTaizhi Liu, Chang-Chih Chen, Woongrae Kim, Linda Milor. mr, 55(9-10):1290-1296, 2015. [doi]

2014

2013

System-level modeling and microprocessor reliability analysis for backend wearout mechanismsChang-Chih Chen, Linda Milor. date 2013: 1615-1620 [doi]

System-level modeling and reliability analysis of microprocessor systemsChang-Chih Chen, Linda Milor. iwasi 2013: 178-183 [doi]

Impact of NBTI/PBTIon SRAMs within microprocessor systems: Modeling, simulation, and analysisChang-Chih Chen, Fahad Ahmed, Linda Milor. mr, 53(9-11):1183-1188, 2013. [doi]

2012

A comparative study of wearout mechanisms in state-of-art microprocessorsChang-Chih Chen, Fahad Ahmed, Linda Milor. iccd 2012: 271-276 [doi]

Backend dielectric reliability simulator for microprocessor systemChang-Chih Chen, Fahad Ahmed, Dae-Hyun Kim, Sung Kyu Lim, Linda Milor. mr, 52(9-10):1953-1959, 2012. [doi]

2005

Construct the Activity Policies of Collaborative Product Design Using the Maturity Level 2 of CMMIKuen Horng Lu, Ya Wen Hsiao, Chang-Chih Chen. ijebm, 3(1):41-57, 2005. [doi]

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