Abstract is missing.
- Fast register consolidation and migration for heterogeneous multi-core processorsElliott Forbes, Eric Rotenberg. 1-8 [doi]
- An adaptive Non-Uniform Loop Tiling for DMA-based bulk data transfers on many-core processorKeni Qiu, Yuanhui Ni, Weigong Zhang, Jing Wang, Xiaoqiang Wu, Chun Jason Xue, Tao Li. 9-16 [doi]
- Enabling technologies for memory compression: Metadata, mapping, and predictionArjun Deb, Paolo Faraboschi, Ali Shafiee, Naveen Muralimanohar, Rajeev Balasubramonian, Robert Schreiber. 17-24 [doi]
- Accelerating pointer chasing in 3D-stacked memory: Challenges, mechanisms, evaluationKevin Hsieh, Samira Manabi Khan, Nandita Vijaykumar, Kevin K. Chang, Amirali Boroumand, Saugata Ghose, Onur Mutlu. 25-32 [doi]
- Scalable memory fabric for silicon interposer-based multi-core systemsItir Akgun, Jia Zhan, Yuangang Wang, Yuan Xie 0001. 33-40 [doi]
- BEOL stack-aware routability prediction from placement using data mining techniquesWei-Ting Jonas Chan, Yang Du, Andrew B. Kahng, Siddhartha Nath, Kambiz Samadi. 41-48 [doi]
- Process variations-aware resistive associative processor designHasan Erdem Yantir, Mohammed E. Fouda, Ahmed M. Eltawil, Fadi J. Kurdahi. 49-55 [doi]
- Extending On-chip Interconnects for rack-level remote resource accessYisong Chang, Ke Zhang, Sally A. McKee, Lixin Zhang, Mingyu Chen, Liqiang Ren, Zhiwei Xu. 56-63 [doi]
- HS-BAS: A hybrid storage system based on band awareness of Shingled Write DiskWenjian Xiao, Huanqing Dong, Liuying Ma, Zhenjun Liu, Qiang Zhang. 64-71 [doi]
- BDR: A Balanced Data Redistribution scheme to accelerate the scaling process of XOR-based Triple Disk Failure Tolerant arraysYanbing Jiang, Chentao Wu, Jie Li, Minyi Guo. 72-79 [doi]
- Using Provenance to boost the Metadata Prefetching in distributed storage systemsGuojin Wu, Yuhui Deng, Xiao Qin. 80-87 [doi]
- Isolation-based decorrelation of stochastic circuitsPai-Shun Ting, John P. Hayes. 88-95 [doi]
- Novel approximate synthesis flow for energy-efficient FIR filterYesung Kang, JaeWoo Kim, Seokhyeong Kang. 96-102 [doi]
- Synthesis design strategies for energy-efficient microprocessorsChing Zhou, Yu-Shiang Lin, Pong-Fei Lu, Bruce M. Fleischer, David J. Frank, Leland Chang. 103-108 [doi]
- Implementing low power digital circuits using flash devicesMonther Abusultan, Sunil P. Khatri. 109-116 [doi]
- Data placement across the cache hierarchy: Minimizing data movement with reuse-aware placementAndreas Sembrant, Erik Hagersten, David Black-Schaffer. 117-124 [doi]
- Dynamic prefetcher reconfiguration for diverse memory architecturesJunghoon Lee, Taehoon Kim, Jaehyuk Huh. 125-132 [doi]
- Ctrl-C: Instruction-Aware Control Loop Based Adaptive Cache Bypassing for GPUsShin-Ying Lee, Carole-Jean Wu. 133-140 [doi]
- A strong arbiter PUF using resistive RAM within 1T-1R memory architectureRekha Govindaraj, Swaroop Ghosh. 141-148 [doi]
- Voting system design pitfalls: Vulnerability analysis and exploitation of a model platformKelvin Ly, Orlando Arias, Jacob Wurm, Khoa Hoang, Kaveh Shamsi, Yier Jin. 149-152 [doi]
- Hardware-based attacks to compromise the cryptographic security of an election systemMohammad-Mahdi Bidmeshki, Gaurav Rajavendra Reddy, Liwei Zhou, Jeyavijayan Rajendran, Yiorgos Makris. 153-156 [doi]
- Cryptographic vote-stealing attacks against a partially homomorphic e-voting architectureNektarios Georgios Tsoutsos, Michail Maniatakos. 157-160 [doi]
- Algorithms for CPU and DRAM DVFS under inefficiency constraintsRizwana Begum, Mark Hempstead, Guru Prasad Srinivasa, Geoffrey Challen. 161-168 [doi]
- Frame-based and thread-based power management for mobile games on HMP platformsNadja Peters, Dominik Fuss, Sangyoung Park, Samarjit Chakraborty. 169-176 [doi]
- nOS: A nano-sized distributed operating system for many-core embedded systemsSimon J. Hollis, Edward Ma, Radu Marculescu. 177-184 [doi]
- WILD: A workload-based learning model to predict dynamic delay of functional unitsXun Jiao, Yu Jiang, Abbas Rahimi, Rajesh K. Gupta. 185-192 [doi]
- A novel simulation based approach for trace signal selection in silicon debugPrabanjan Komari, Ranga Vemuri. 193-200 [doi]
- CHARM: A checkpoint-based resource management framework for reliable multicore computing in the dark silicon eraVenkata Yaswanth Raparti, Nishit Ashok Kapadia, Sudeep Pasricha. 201-208 [doi]
- Refresh-aware loop scheduling for high performance low power volatile STT-RAMKeni Qiu, Junpeng Luo, Zhiyao Gong, Weigong Zhang, Jing Wang, Yuanchao Xu, Tao Li, Chun Jason Xue. 209-216 [doi]
- Understanding and alleviating intra-die and intra-DIMM parameter variation in the memory systemMeysam Taassori, Ali Shafiee, Rajeev Balasubramonian. 217-224 [doi]
- SRAM stability analysis for different cache configurations due to Bias Temperature Instability and Hot Carrier InjectionTaizhi Liu, Chang-Chih Chen, Jiadong Wu, Linda S. Milor. 225-232 [doi]
- Fluid Pipelines: Elastic circuitry meets Out-of-Order executionRafael Trapani Possignolo, Elnaz Ebrahimi, Haven Skinner, Jose Renau. 233-240 [doi]
- Power-aware virtual machine mapping in the data-center-on-a-chip paradigmXue Lin, Yuankun Xue, Paul Bogdan, Yanzhi Wang, Siddharth Garg, Massoud Pedram. 241-248 [doi]
- Tuning Stencil codes in OpenCL for FPGAsQi Jia, Huiyang Zhou. 249-256 [doi]
- Hardware thread reordering to boost OpenCL throughput on FPGAsAmir Momeni, Hamed Tabkhi, Gunar Schirner, David R. Kaeli. 257-264 [doi]
- Energy-aware scheduling of conditional task graphs with deadlines on MPSoCsUmair Ullah Tariq, Hui Wu. 265-272 [doi]
- Design automation of multiple-demand mixture preparation using a K-array rotary mixer on digital microfluidic biochipsSatendra Kumar, Ankur Gupta 0002, Sudip Roy 0001, Bhargab B. Bhattacharya. 273-280 [doi]
- Luminescent solar concentrator-based photovoltaic reconfiguration for hybrid and plug-in electric vehiclesCaiwen Ding, Hongjia Li, Weiwei Zheng, Yanzhi Wang, Naehyuck Chang, Xue Lin. 281-288 [doi]
- Dynamic converter reconfiguration for near-threshold non-volatile processors using in-door energy harvestingCaiwen Ding, Hongjia Li, Jingtong Hu, Yongpan Liu, Yanzhi Wang. 289-295 [doi]
- Adaptive and flexible key-value stores through soft data partitioningByungchul Hong, Yongkee Kwon, Jung Ho Ahn, John Kim. 296-303 [doi]
- Tolerating more hard errors in MLC PCMs using compressionMajid Jalili 0001, Hamid Sarbazi-Azad. 304-311 [doi]
- Exploiting cache coherence for effective on-the-fly data tracing in multicoresMounika Ponugoti, Aleksandar Milenkovic. 312-319 [doi]
- CNN-MERP: An FPGA-based memory-efficient reconfigurable processor for forward and backward propagation of convolutional neural networksXushen Han, Dajiang Zhou, Shihao Wang, Shinji Kimura. 320-327 [doi]
- Lumos+: Rapid, pre-RTL design space exploration on accelerator-rich heterogeneous architectures with reconfigurable logicLiang Wang, Kevin Skadron. 328-335 [doi]
- Efficient processor allocation in a reconfigurable CMP architecture for dark silicon eraFatemeh Aghaaliakbari, Mohaddeseh Hoveida, Mohammad Arjomand, Majid Jalili 0001, Hamid Sarbazi-Azad. 336-343 [doi]
- TESLA: Using microfluidics to thermally stabilize 3D stacked STT-RAM cachesMajed Valad Beigi, Gokhan Memik. 344-347 [doi]
- Dynamic single and Dual Rail spin transfer torque look up tables with enhanced robustness under CMOS and MTJ process variationsAliyar Attaran, Hassan Salmani, Houman Homayoun, Hamid Mahmoodi. 348-351 [doi]
- DOART: A low-power and low-latency Network-on-ChipWen Zong, Qiang Xu. 352-355 [doi]
- Error behaviors testing with temperature and magnetism dependency for MRAMXin Shi, Fei Wu, Xidong Guan, Changsheng Xie. 356-359 [doi]
- AIBA: An Automated Intra-cycle Behavioral Analysis for SystemC-based design explorationMehran Goli, Jannis Stoppe, Rolf Drechsler. 360-363 [doi]
- A fast, fully verifiable, and hardware predictable ASIC design methodologyPing-Lin Yang, Malgorzata Marek-Sadowska. 364-367 [doi]
- Memos: A full hierarchy hybrid memory management frameworkLei Liu, Hao Yang, Yong Li, Mengyao Xie, Lian Li, Chenggang Wu. 368-371 [doi]
- Relinquishment coherence for enhancing directory efficiency in chip multiprocessorsWei Shu, Nian-Feng Tzeng. 372-375 [doi]
- Hippogriff: Efficiently moving data in heterogeneous computing systemsYang Liu, Hung-Wei Tseng, Mark Gahagan, Jing Li, Yanqin Jin, Steven Swanson. 376-379 [doi]
- IACM: Integrated adaptive cache management for high-performance and energy-efficient GPGPU computingKyu Yeun Kim, Jinsu Park, Woongki Baek. 380-383 [doi]
- SPMario: Scale up MapReduce with I/O-Oriented Scheduling for the GPUYang Liu, Hung-Wei Tseng, Steven Swanson. 384-387 [doi]
- "Stubborn" strategy to mitigate remaining cache missesHayato Nomura, Hiroyuki Katchi, Hidetsugu Irie, Shuichi Sakai. 388-391 [doi]
- A new coding scheme for fault tolerant 4-phase delay-insensitive codesFlorian Huemer, Jakob Lechner, Andreas Steininger. 392-395 [doi]
- Scalable memory architecture for soft-core processorsTiago T. Jost, Gabriel L. Nazar, Luigi Carro. 396-399 [doi]
- Wireless Network-on-Chip analysis of propagation technique for on-chip communicationVasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin, Kapil R. Dandekar. 400-403 [doi]
- Quantifying the difference in resource demand among classic and modern NoC workloadsAmirhossein Mirhosseini, Mohammad Sadrosadati, Maryam Zare, Hamid Sarbazi-Azad. 404-407 [doi]
- Machine learning classifiers using stochastic logicYin Liu, Hariharasudhan Venkataraman, Zisheng Zhang, Keshab K. Parhi. 408-411 [doi]
- A novel hardware hash unit design for modern microprocessorsAbbas Fairouz, Monther Abusultan, Sunil P. Khatri. 412-415 [doi]
- Exploring static and dynamic flash-based FPGA design topologiesMonther Abusultan, Sunil P. Khatri. 416-419 [doi]
- Concurrent Migration of Multiple Pages in software-managed hybrid main memorySantiago Bock, Bruce R. Childers, Rami G. Melhem, Daniel Mossé. 420-423 [doi]
- How logic masking can improve path delay analysis for Hardware Trojan detectionArash Nejat, David Hély, Vincent Beroulle. 424-427 [doi]
- CyHOP: A generic framework for real-time power-performance optimization in networked wearable motion sensorsRamin Fallahzadeh, Hassan Ghasemzadeh. 428-431 [doi]
- Parallelizing Latent Semantic Indexing using an FPGA-based architectureXinying Wang, Joseph Zambreno. 432-435 [doi]
- CloudSocket: Smart grid platform for datacentersSeil Lee, Hanjoo Kim, Seongsik Park, Sei Joon Kim, Hyeokjun Choe, Chang-Sung Jeong, Sungroh Yoon. 436-439 [doi]
- Shuffling across rounds: A lightweight strategy to counter side-channel attacksSikhar Patranabis, Debapriya Basu Roy, Praveen Kumar Vadnala, Debdeep Mukhopadhyay, Santosh Ghosh. 440-443 [doi]
- CCAS: Contention and congestion aware switch allocation for network-on-chipsCunlu Li, Dezun Dong, Xiangke Liao, Fei Lei, Ji Wu. 444-447 [doi]
- SRAM memory margin probability failure estimation using Gaussian Process regressionManish Rana, Ramon Canal, Jie Han, Bruce F. Cockburn. 448-451 [doi]
- Towards a timing attack aware high-level synthesis of integrated circuitsSteffen Peter, Tony Givargis. 452-455 [doi]
- A model for Application Slowdown Estimation in on-chip networks and its use for improving system fairness and performanceXi-Yue Xiang, Saugata Ghose, Onur Mutlu, Nian-Feng Tzeng. 456-463 [doi]
- Pull-off buffer: Borrowing cache space to avoid deadlock for fault-tolerant NoC routingAiran Shao, Dongsheng Wang, Haixia Wang. 464-471 [doi]
- A heterogeneous low-cost and low-latency Ring-Chain network for GPGPUsXia Zhao, Sheng Ma, Chen Li 0015, Lieven Eeckhout, Zhiying Wang. 472-479 [doi]
- Energy aware routing of multi-level Network-on-Chip trafficVasil Pano, Isikcan Yilmaz, Ankit More, Baris Taskin. 480-486 [doi]
- A single-inductor-cascaded-stage topology for high conversion ratio boost regulatorKhondker Zakir Ahmed, Saibal Mukhopadhyay. 487-491 [doi]
- Data-Pattern enabled Self-Recovery multimedia storage system for near-threshold computingNa Gong, Jonathon Edstrom, Dongliang Chen, Jinhui Wang. 492-498 [doi]
- A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOSSamira Ataei, James E. Stine, Matthew R. Guthaus. 499-506 [doi]
- A statistical critical path monitor in 14nm CMOSBruce M. Fleischer, Christos Vezyrtzis, Karthik Balakrishnan, Keith A. Jenkins. 507-511 [doi]
- ONAC: Optimal number of active cores detector for energy efficient GPU computingXian Zhu, Mihir Awatramani, Diane T. Rover, Joseph Zambreno. 512-519 [doi]
- Thermal-aware 3D design for side-channel information leakagePeng Gu, Dylan Stow, Russell Barnes, Eren Kursun, Yuan Xie 0001. 520-527 [doi]
- Improving performance per Watt of non-monotonic Multicore Processors via bottleneck-based online program phase classificationSudarshan Srinivasan, Israel Koren, Sandip Kundu. 528-535 [doi]
- BADGR: A practical GHR implementation for TAGE branch predictorsDavid J. Schlais, Mikko H. Lipasti. 536-543 [doi]
- Unveiling difficult bugs in address translation caching arrays for effective post-silicon validationGeorge Papadimitriou, Dimitris Gizopoulos, Athanasios Chatzidimitriou, Tom Kolan, Anatoly Koyfman, Ronny Morad, Vitali Sokhin. 544-551 [doi]
- Chain-based pseudorandom tests for pre-silicon verification of CMP memory systemsGabriel A. G. Andrade, Marleson Graf, Luiz C. V. dos Santos. 552-559 [doi]
- A novel approach to parameterized verification of cache coherence protocolsYongjian Li, Kaiqiang Duan, Yi Lv, Jun Pang, Shaowei Cai. 560-567 [doi]
- A readback based general debugging framework for soft-core processorsChanggong Li, Alexander Schwarz, Christian Hochberger. 568-575 [doi]
- MFAP: Fair Allocation between fully backlogged and non-fully backlogged applicationsYan Sui, Chun Yang, Dong Tong, Xianhua Liu, Xu Cheng. 576-583 [doi]
- Strategies for optimal operating point selection in timing speculative processorsOmid Assare, Rajesh K. Gupta. 584-591 [doi]
- Efficient mode changes in multi-mode systemsAkramul Azim, Sebastian Fischmeister. 592-599 [doi]
- FPGA Trust Zone: Incorporating trust and reliability into FPGA designsVinayaka Jyothi, Manasa Thoonoli, Richard Stern, Ramesh Karri. 600-605 [doi]
- Guided lightweight Software test qualification for IP integration using Virtual PrototypesDaniel Große, Hoang M. Le, Muhammad Hassan, Rolf Drechsler. 606-613 [doi]
- MASkIt: Soft error rate estimation for combinational circuitsMarti Anglada, Ramon Canal, Juan L. Aragón, Antonio González 0001. 614-621 [doi]
- Generating efficient and high-quality pseudo-random behavior on Automata ProcessorsJack Wadden, Nathan Brunelle, Ke Wang, Mohamed El-Hadedy, Gabriel Robins, Mircea Stan, Kevin Skadron. 622-629 [doi]
- Speculative path power estimation using trace-driven simulations during high-level design phaseSaumya Chandra, Ramkumar Jayaseelan, Ravi Bhargava. 630-637 [doi]
- ×86 computer architecture simulators: A comparative studyAyaz Akram, Lina Sawalha. 638-645 [doi]
- DLL: A dynamic latency-aware load-balancing strategy in 2.5D NoC architectureChen Li 0015, Sheng Ma, Lu Wang, Zicong Wang, Xia Zhao, Yang Guo. 646-653 [doi]
- VARIUS-TC: A modular architecture-level model of parametric variation for thin-channel switchesS. Karen Khatamifard, Michael Resch, Nam Sung Kim, Ulya R. Karpuzcu. 654-661 [doi]
- CNFET-based high throughput register file architectureTianjian Li, Li Jiang, Naifeng Jing, Nam Sung Kim, Xiaoyao Liang. 662-669 [doi]
- Stochastic neuromorphic learning machines for weakly labeled dataEmre Neftci. 670-673 [doi]
- Design techniques of eNVM-enabled neuromorphic computing systemsChang Song, Beiye Liu, Chenchen Liu, Hai Li, Yiran Chen. 674-677 [doi]
- DSCNN: Hardware-oriented optimization for Stochastic Computing based Deep Convolutional Neural NetworksZhe Li, Ao Ren, Ji Li, Qinru Qiu, Yanzhi Wang, Bo Yuan. 678-681 [doi]
- Ultra-low energy security circuits for IoT applicationsSudhir Satpathy, Sanu Mathew, Vikram Suresh, Ram Krishnamurthy. 682-685 [doi]
- What does ultra low power requirements mean for side-channel secure cryptography?Monodeep Kar, Arvind Singh, Anand Rajan, Vivek De, Saibal Mukhopadhyay. 686-689 [doi]
- The power play: Security-energy trade-offs in the IoT regimeSandip Ray, Tamzidul Hoque, Abhishek Basak, Swarup Bhunia. 690-693 [doi]