Table of Contents

• Extracting effective functional tests from commercial programsSreekumar Vadakke Kodakara, Mehul V. Sagar, Joel Yuen. 1-6 [doi]
• Horizontal-FPN fault coverage improvement in production test of CMOS imagersR. Fei, Jocelyn Moreau, S. Mir, A. Marcellin, C. Mandier, E. Huss, G. Palmigiani, P. Vitrou, Thomas Droniou. 1-6 [doi]
• Test compaction by test cube merging for four-way bridging faultsIrith Pomeranz. 1-6 [doi]
• Testing cross wire opens within complex gatesChao Han, Adit D. Singh. 1-6 [doi]
• A multi-layered methodology for defect-tolerance of datapath modules in processorsHsunwei Hsiung, Sandeep K. Gupta. 1-6 [doi]
• Low cost high frequency signal synthesis: Application to RF channel interference testingXian Wang, Debashis Banerjee, Abhijit Chatterjee. 1-6 [doi]
• Yield prognosis for fab-to-fab product migrationAli Ahmadi, Ke Huang, Amit Nahar, Bob Orr, Michael Pas, John M. Carulli, Yiorgos Makris. 1-6 [doi]
• MBIST and statistical hypothesis test for time dependent dielectric breakdowns due to GOBD vs. BTDDB in an SRAM arrayWoongrae Kim, Chang-Chih Chen, Soonyoung Cha, Linda Milor. 1-6 [doi]
• Panel: When will the cost of dependability end innovation in computer design?Valeria Bertacco. 1 [doi]
• Innovative practices session 1C: New technologies, new challenges - 1 [3 presentations]Paul Tracey. 1 [doi]
• No Fault Found: The root causeErik Larsson, Bill Eklow, Scott Davidsson, Rob Aitken, Artur Jutman, Christophe Lotz. 1 [doi]
• A low cost jitter separation and characterization methodLi Xu, Yan Duan, Degang Chen. 1-5 [doi]
• Improving the accuracy of defect diagnosis by considering reduced diagnostic informationIrith Pomeranz. 1-6 [doi]
• Multi-cycle Circuit Parameter Independent ATPG for interconnect open defectsDominik Erb, Karsten Scheibler, Matthias Sauer, Sudhakar M. Reddy, Bernd Becker. 1-6 [doi]
• Scalability study of PSANDE: Power supply analysis for noise and delay estimationSushmita Kadiyala Rao, Bharath Shivashankar, Ryan Robucci, Nilanjan Banerjee, Chintan Patel. 1-6 [doi]
• Improving diagnosis resolution of a fault detection test setAndreas Riefert, Matthias Sauer, Sudhakar M. Reddy, Bernd Becker. 1-6 [doi]
• Ultrafast stimulus error removal algorithm for ADC linearity testTao Chen, Degang Chen. 1-5 [doi]
• Special session 12B: Panel: IOT - Reliable? Secure? Or death by a billion cuts?Sreekumar V. Kodakara, Suriya Natarajan. 1 [doi]
• Special session: Hot topics: Statistical test methodsManuel J. Barragan, Gildas Leger, Florence Azaïs, Ronald D. Blanton, Adit D. Singh, Stephen Sunter. 1-2 [doi]
• Integral impact of BTI and voltage temperature variation on SRAM sense amplifierInnocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Halil Kukner, Pieter Weckx, Praveen Raghavan, Francky Catthoor. 1-6 [doi]
• Special session 8C: E.J. McCluskey doctoral thesis award semi-finalMichele Portolan, K. Huang. 1-2 [doi]
• A call to action: Securing IEEE 1687 and the need for an IEEE test Security StandardJennifer Dworak, Al Crouch. 1-4 [doi]
• Innovative practices session 11C: Advanced scan methodologies [3 presentations]Janusz Rajski, Nilanjan Mukherjee. 1 [doi]
• Innovative practices session 5C: Advancements in test -keeping moore moving!Enamul Amyeen. 1 [doi]
• Signature oriented model pruning to facilitate multi-threaded processors debuggingFatemeh Refan, Bijan Alizadeh, Zainalabedin Navabi. 1-6 [doi]
• Innovative practices session 7C: Mixed signal test and debugSuriya Natarajan. 1 [doi]
• Fault modeling and testing of 1T1R memristor memoriesYong-Xiao Chen, Jin-Fu Li. 1-6 [doi]
• Abstraction-based relation mining for functional test generationKelson Gent, Michael S. Hsiao. 1-6 [doi]
• Pulse shrinkage based pre-bond through silicon vias test in 3D ICChang Hao, Huaguo Liang. 1-6 [doi]
• ForewordClaude Thibeault. 1 [doi]
• A definition of the number of detections for faults with single tests in a compact scan-based test setIrith Pomeranz. 1-6 [doi]
• UPF-based formal verification of low power techniques in modern processorsReza Sharafinejad, Bijan Alizadeh, Masahiro Fujita. 1-6 [doi]
• Panel: Is design-for-security the new DFT?Rob Aitken. 1 [doi]
• TMO: A new class of attack on cipher misusing test infrastructureSk Subidh Ali, Ozgur Sinanoglu. 1-4 [doi]
• Efficient built-in self test of regular logic characterization vehiclesBen Niewenhuis, Ronald D. Blanton. 1-6 [doi]
• Robust counterfeit PCB detection exploiting intrinsic trace impedance variationsFengchao Zhang, Andrew Hennessy, Swarup Bhunia. 1-6 [doi]
• Random pattern generation for post-silicon validation of DDR3 SDRAMHao-Yu Yang, Shih-Hua Kuo, Tzu-Hsuan Huang, Chi-Hung Chen, Chris Lin, Mango Chia-Tso Chao. 1-6 [doi]
• Automated testing of mixed-signal integrated circuits by topology modificationAnthony Coyette, Baris Esen, Ronny Vanhooren, Wim Dobbelaere, Georges Gielen. 1-6 [doi]
• In-depth soft error vulnerability analysis using synthetic benchmarksShahrzad Mirkhani, Balavinayagam Samynathan, Jacob A. Abraham. 1-6 [doi]
• Keynote address: New opportunities in the internet of thingsYankin Tanurhan. 1 [doi]
• PPB: Partially-working processors binning for maximizing wafer utilizationDa Cheng, Sandeep K. Gupta. 1-6 [doi]
• Innovative practices session 3C: Advances in silicon debug & diagnosisMike Ricchetti. 1 [doi]
• Panel: Analog/RF BIST: Are we there yet?Sule Ozev, Linda Milor. 1 [doi]
• Improving accuracy of on-chip diagnosis via incremental learningXuanle Ren, Mitchell Martin, Ronald D. Blanton. 1-6 [doi]
• Capacitive Coupling Mitigation for TSV-based 3D ICsAshkan Eghbal, Pooria M. Yaghini, Nader Bagherzadeh. 1-6 [doi]
• Fault diagnosis for flow-based microfluidic biochipsKai Hu, Bhargab B. Bhattacharya, Krishnendu Chakrabarty. 1-6 [doi]
• Test vector omission with minimal sets of simulated faultsIrith Pomeranz. 1-6 [doi]
• Statistical techniques for predicting system-level failure using stress-test dataHarry H. Chen, Shih-Hua Kuo, Jonathan Tung, Mango Chia-Tso Chao. 1-6 [doi]
• Testing of 3D-stacked ICs with hard- and soft-dies - a Particle Swarm Optimization based approachRajit Karmakar, Aditya Agarwal, Santanu Chattopadhyay. 1-6 [doi]
• An early prediction methodology for aging sensor insertion to assure safe circuit operation due to NBTI agingAndres Gomez, Leticia Poehls, Fabian Vargas, Víctor H. Champac. 1-6 [doi]
• Disturbance-free BIST for loop characterization of DC-DC buck convertersNavankur Beohar, Priyanka Bakliwal, Sidhanto Roy, Debashis Mandal, Philippe Adell, Bert Vermeire, Bertan Bakkaloglu, Sule Ozev. 1-6 [doi]
• Resiliency challenges in sub-10nm technologiesRob Aitken, Ethan H. Cannon, Mondira Pant, Mehdi Baradaran Tahoori. 1-4 [doi]
• Field, experimental, and analytical data on large-scale HPC systems and evaluation of the implications for exascale system designNathan DeBardeleben, Sean Blanchard, David Kaeli, Paolo Rech. 1-2 [doi]
• Enabling unauthorized RF transmission below noise floor with no detectable impact on primary communication performanceDoohwang Chang, Bertan Bakkaloglu, Sule Ozev. 1-4 [doi]
• Innovative practices session 2C: New technologies, new challenges - 2Suraj Sindia. 1 [doi]
• At-Product-Test Dedicated Adaptive supply-resonance suppressionKohki Taniguchi, Noriyuki Miura, Taisuke Hayashi, Makoto Nagata. 1-6 [doi]
• A robust digital sensor IP and sensor insertion flow for in-situ path timing slack monitoring in SoCsMehdi Sadi, LeRoy Winemberg, Mark Tehranipoor. 1-6 [doi]
• ExTest scheduling for 2.5D system-on-chip integrated circuitsRan Wang, Guoliang Li, Rui Li, Jun Qian, Krishnendu Chakrabarty. 1-6 [doi]
• Rapid online fault recovery for cyber-physical digital microfluidic biochipsChristopher Jaress, Philip Brisk, Daniel Grissom. 1-6 [doi]
• 3D microelectronic with BEOL compatible devicesD. Drouin, M. A.-Bounouar, G. Droulers, M. Labalette, M. Pioro-Ladriere, A. Souifi, S. Ecoffey. 1 [doi]
• Impact of parameter variations on FinFET faultsGurgen Harutyunyan, G. Tshagharyan, Yervant Zorian. 1-4 [doi]
• Memory repair for high defect densitiesMichael Nicolaidis, Panagiota Papavramidou. 1-4 [doi]