Seyed Nematollah Ahmadyan, Jayanand Asok Kumar, Shobha Vasudevan. Runtime verification of nonlinear analog circuits using incremental time-augmented RRT algorithm. In Enrico Macii, editor, Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013. pages 21-26, EDA Consortium San Jose, CA, USA / ACM DL, 2013. [doi]
Abstract is missing.