Abstract is missing.
- Temporal Logic Model Checking: Two Techniques for Avoiding the State Explosion ProblemEdmund M. Clarke. 1
- Automatic Verification of Extensions of Hardware DescriptionsHans Eveking. 2-12
- PAPETRI: Environment for the Analysis of Petri NetsGérard Berthelot, Colette Johnen, Laure Petrucci. 13-22
- Verifying Temporal Properties of Sequential Machines Without Building their State DiagramsOlivier Coudert, Jean Christophe Madre, Christian Berthet. 23-32
- Formal Verification of Digital Circuits Using Symbolic Ternary System ModelsRandal E. Bryant, Carl-Johan H. Seger. 33-43
- Vectorized Model Checking for Computation Tree LogicHiromi Hiraishi, Shintaro Meki, Kiyoharu Hamaguchi. 44-53
- Introduction to a Computational Theory and Implementation of Sequential Hardware EquivalenceCarl Pixley. 54-64
- Auto/AutographValérie Roy, Robert de Simone. 65-75
- A Data Path Verifier for Register Transfer Level Using Temporal Logic Language TokioHiroshi Nakamura, Yuji Kukimoto, Masahiro Fujita, Hidehiko Tanaka. 76-85
- The Use of Model Checking in ATPG for Sequential CircuitsPaolo Camurati, M. Gilli, Paolo Prinetto, Matteo Sonza Reorda. 86-95
- Compositional Design and Verification of Communication Protocols, Using Labelled Petri NetsJean Christophe Lloret, Pierre Azéma, François Vernadat. 96-105
- Issues Arising in the Analysis of L.0Linda A. Ness. 106-115
- Automated RTL Verification Based on Predicate CalculusMichel Langevin. 116-125
- On Using Protean To Verify ISO FTAM ProtocolRichard Lai, Ken R. Parker, Tharam S. Dillon. 126-135
- Quantitative Temporal ReasoningE. Allen Emerson, Aloysius K. Mok, A. Prasad Sistla, Jai Srinivasan. 136-145
- Using Partial-Order Semantics to Avoid the State Explosion Problem in Asynchronous SystemsDavid K. Probst, Hon F. Li. 146-155
- A Stubborn Attack On State ExplosionAntti Valmari. 156-165
- Using Optimal Simulations to Reduce Reachability GraphsRyszard Janicki, Maciej Koutny. 166-175
- Using Partial Orders to Improve Automatic Verification MethodsPatrice Godefroid. 176-185
- Compositional Minimization of Finite State SystemsSusanne Graf, Bernhard Steffen. 186-196
- Minimal Model GenerationAhmed Bouajjani, Jean-Claude Fernandez, Nicolas Halbwachs. 197-203
- A Context Dependent Equivalence Relation Between Kripke StructuresBernhard Josko. 204-213
- The Modular Framework of Computer-Aided VerificationGil Shurek, Orna Grumberg. 214-223
- Verifying Liveness Properties by Verifying Safety PropertiesJerry R. Burch. 224-232
- Memory Efficient Algorithms for the Verification of Temporal PropertiesCostas Courcoubetis, Moshe Y. Vardi, Pierre Wolper, Mihalis Yannakakis. 233-242
- A Unified Approach to the Deadlock Detection Problem in Networks of Communicating Finite State MachinesWuxu Peng, S. Purushothaman. 243-252
- Branching Time Regular Temporal Logic for Model Checking with Linear Time ComplexityKiyoharu Hamaguchi, Hiromi Hiraishi, Shuzo Yajima. 253-262
- The Algebraic Feedback Product of AutomataVictor Yodaiken. 263-271
- Synthesizing Processes and Schedulers from Temporal SpecificationsHoward Wong-Toi, David L. Dill. 272-281
- Task-Driven Supervisory Control of Discrete Event SystemsChristian H. Golaszewski, Robert P. Kurshan. 282-291
- A Proof Lattice-Based Technique for Analyzing Liveness of Resource ControllersUgo A. Buy, Robert Moll. 292-301
- Verification of a Multiprocessor Cache Protocol Using Simulation Relations and Higher-Order LogicPaul Loewenstein, David L. Dill. 302-311
- Computer Assistance for Program RefinementDavid A. Carrington, K. A. Robinson. 312-321
- Program Verification by Symbolic Execution of Hyperfinite Ideal MachinesJames M. Morris, Mark Howard. 322-332
- Extension of the Karp and Miller Procedure to Lotos SpecificationsMichel Barbeau, Gregor von Bochmann. 333-342
- An Algebra for Delay-Insensitive CircuitsMark B. Josephs, Jan Tijmen Udding. 343-352
- Finiteness Conditions and Structural Construction of Automata for All Process AlgebrasEric Madelaine, Didier Vergamini. 353-363
- On Automatically Explaining Bisimulation InequivalenceRance Cleaveland. 364-372