Abstract is missing.
- Comprehensive frequency-dependent substrate noise analysis using boundary element methodsHongmei Li, Jorge Carballido, Harry H. Yu, Vladimir I. Okhmatovski, Elyse Rosenbaum, Andreas C. Cangellaris. 2-9 [doi]
- Theoretical and practical validation of combined BEM/FEM substrate resistance modelingEelco Schrik, Patrick Dewilde, N. P. van der Meijs. 10-15 [doi]
- Implicit treatment of substrate and power-ground losses in return-limited inductance extractionDipak Sitaram, Yu Zheng, Kenneth L. Shepard. 16-22 [doi]
- Minimizing power across multiple technology and design levelsTakayasu Sakurai. 24-27 [doi]
- Optimization and control of ::::V::::::DD:: and ::::V::::::TH:: for low-power, high-speed CMOS designTadahiro Kuroda. 28-34 [doi]
- Methods for true power minimizationRobert W. Brodersen, Mark Horowitz, Dejan Markovic, Borivoje Nikolic, Vladimir Stojanovic. 35-42 [doi]
- A novel framework for multilevel routing considering routability and performanceShih-Ping Lin, Yao-Wen Chang. 44-50 [doi]
- An enhanced multilevel routing systemJason Cong, Min Xie, Yan Zhang. 51-58 [doi]
- Track assignment: a desirable intermediate step between global routing and detailed routingShabbir H. Batterywala, Narendra V. Shenoy, William Nicholls, Hai Zhou. 59-66 [doi]
- ECO algorithms for removing overlaps between power rails and signal wiresHua Xiang, Kai-Yuan Chao, D. F. Wong. 67-74 [doi]
- Fast seed computation for reseeding shift register in test pattern compressionNahmsuk Oh, Rohit Kapur, Thomas W. Williams. 76-81 [doi]
- On undetectable faults in partial scan circuitsIrith Pomeranz, Sudhakar M. Reddy. 82-86 [doi]
- Conflict driven techniques for improving deterministic test pattern generationChen Wang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski. 87-93 [doi]
- On theoretical and practical considerations of path selection for delay fault testingJing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng. 94-100 [doi]
- Interface specification for reconfigurable componentsSatnam Singh. 102-109 [doi]
- Interconnect-aware high-level synthesis for low powerLin Zhong, Niraj K. Jha. 110-117 [doi]
- Predictability: definition, ananlysis and optimizationAnkur Srivastava, Majid Sarrafzadeh. 118-121 [doi]
- Simplifying Boolean constraint solving for random simulation-vector generationJun Yuan, Ken Albin, Adnan Aziz, Carl Pixley. 123-127 [doi]
- Specifying and verifying imprecise sequential datapaths by Arithmetic TransformsKatarzyna Radecka, Zeljko Zilic. 128-131 [doi]
- Convertibility verification and converter synthesis: two faces of the same coinRoberto Passerone, Luca de Alfaro, Thomas A. Henzinger, Alberto L. Sangiovanni-Vincentelli. 132-139 [doi]
- Subthreshold leakage modeling and reduction techniquesJames Kao, Siva Narendra, Anantha Chandrakasan. 141-148 [doi]
- Symbolic pointer analysisJianwen Zhu. 150-157 [doi]
- Dynamic compilation for energy adaptationPriya Unnikrishnan, Guangyu Chen, Mahmut T. Kandemir, D. R. Mudgett. 158-163 [doi]
- Hardware/software partitioning of software binariesGreg Stitt, Frank Vahid. 164-170 [doi]
- A novel net weighting algorithm for timing-driven placementTim (Tianming) Kong. 172-176 [doi]
- Timing-driven placement using design hierarchy guided constraint generationXiaojian Yang, Bo-Kyung Choi, Majid Sarrafzadeh. 177-180 [doi]
- Multi-objective circuit partitioning for cutsize and path-based delay minimizationCristinel Ababei, Navaratnasothie Selvakkumaran, Kia Bazargan, George Karypis. 181-185 [doi]
- A hybrid ASIC and FPGA architecturePaul S. Zuchowski, Christopher B. Reynolds, Richard J. Grupp, Shelly G. Davis, Brendan Cremen, Bill Troxel. 187-194 [doi]
- Managing power and performance for System-on-Chip designs using Voltage IslandsDavid E. Lackey, Paul S. Zuchowski, Thomas R. Bednar, Douglas W. Stout, Scott W. Gould, John M. Cohn. 195-202 [doi]
- Sub-90nm technologies: challenges and opportunities for CADTanay Karnik, Shekhar Borkar, Vivek De. 203-206 [doi]
- A local circuit topology for inductive parasiticsAndrea Pacelli. 208-214 [doi]
- INDUCTWISE: inductance-wise interconnect simulator and extractorTsung-Hao Chen, Clement Luk, Hyungsuk Kim, Charlie Chung-Ping Chen. 215-220 [doi]
- A precorrected-FFT method for simulating on-chip inductanceHaitian Hu, David Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar. 221-227 [doi]
- On the difference between two widely publicized methods for analyzing oscillator phase behaviorPiet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen. 229-233 [doi]
- A behavioral simulation tool for continuous-time delta sigma modulatorsKenneth Francken, Martin Vogels, Ewout Martens, Georges G. E. Gielen. 234-239 [doi]
- Making Fourier-envelope simulation robustJaijeet S. Roychowdhury. 240-245 [doi]
- Optimal buffered routing path constructions for single and multiple clock domain systemsSoha Hassoun, Charles J. Alpert, Meera Thiagarajan. 247-253 [doi]
- Shaping interconnect for uniform current densityMuzhou Shao, D. F. Wong, Youxin Gao, Li-Pen Yuan, Huijing Cao. 254-259 [doi]
- Non-tree routing for reliability and yield improvementAndrew B. Kahng, Bao Liu, Ion I. Mandoiu. 260-266 [doi]
- Concurrent flip-flop and repeater insertion for high performance integrated circuitsPasquale Cocchini. 268-273 [doi]
- Throughput-driven IC communication fabric synthesisTao Lin, Lawrence T. Pileggi. 274-279 [doi]
- Repeater insertion and wire sizing optimization for throughput-centric VLSI global interconnectsHarshit K. Shah, Pun Shiu, Brian Bell, Mamie Aldredge, Namarata Sopory, Jeff Davis. 280-284 [doi]
- Test-model based hierarchical DFT synthesisSanjay Ramnath, Frederic Neuveux, Mokhtar Hirech, Felix Ng. 286-293 [doi]
- Characteristic faults and spectral information for logic BISTXiaoding Chen, Michael S. Hsiao. 294-298 [doi]
- A novel scan architecture for power-efficient, rapid testOzgur Sinanoglu, Alex Orailoglu. 299-303 [doi]
- Optimization of a fully integrated low power CMOS GPS receiverPeter J. Vancorenland, Philippe Coppejans, Wouter De Cock, Paul Leroux, Michiel Steyaert. 305-308 [doi]
- Analysis and optimization of substrate noise coupling in single-chip RF transceiver designAdil Koukab, Kaustav Banerjee, Michel J. Declercq. 309-316 [doi]
- Design of pipeline analog-to-digital converters via geometric programmingMaria del Mar Hershenson. 317-324 [doi]
- Proximity templates for modeling of skin and proximity effects on packages and high frequency interconnectLuca Daniel, Alberto L. Sangiovanni-Vincentelli, Jacob White. 326-333 [doi]
- Transmission line design of clock treesRafael Escovar, Roberto Suaya. 334-340 [doi]
- On-chip interconnect modeling by wire duplicationGuoan Zhong, Cheng-Kok Koh, Kaushik Roy. 341-346 [doi]
- A Case for CMOS/nano co-designMatthew M. Ziegler, Mircea R. Stan. 348-352 [doi]
- Reversible logic circuit synthesisVivek V. Shende, Aditya K. Prasad, Igor L. Markov, John P. Hayes. 353-360 [doi]
- Extraction and LVS for mixed-domain integrated MEMS layoutsBikram Baidya, Tamal Mukherjee. 361-366 [doi]
- Schematic-based lumped parameterized behavioral modeling for suspended MEMSQi Jing, Tamal Mukherjee, Gary K. Fedder. 367-373 [doi]
- Standby power optimization via transistor sizing and dual threshold voltage assignmentMahesh Ketkar, Sachin S. Sapatnekar. 375-378 [doi]
- Power efficiency of voltage scaling in multiple clock, multiple voltage coresAnoop Iyer, Diana Marculescu. 379-386 [doi]
- Optimized power-delay curve generation for standard cell ICsMiodrag Vujkovic, Carl Sechen. 387-394 [doi]
- Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing stepHiran Tennakoon, Carl Sechen. 395-402 [doi]
- A Markov chain sequence generator for power macromodelingXun Liu, Marios C. Papaefthymiou. 404-411 [doi]
- Circuit power estimation using pattern recognition techniquesLipeng Cao. 412-417 [doi]
- Estimation of signal arrival times in the presence of delay noiseSarvesh Bhardwaj, Sarma B. K. Vrudhula, David Blaauw. 418-422 [doi]
- CAD computation for manufacturability: can we save VLSI technology from itself?Mark A. Lavin, Lars Liebmann. 424-431 [doi]
- Molecular electronics: devices, systems and tools for gigagate, gigabit chipsMichael Butts, André DeHon, Seth Copen Goldstein. 433-440 [doi]
- Conflict driven learning in a quantified Boolean Satisfiability solverLintao Zhang, Sharad Malik. 442-449 [doi]
- Generic ILP versus specialized 0-1 ILP: an updateFadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah. 450-457 [doi]
- Binary time-frame expansionFarzan Fallah. 458-464 [doi]
- Fast methods for simulation of biomolecule electrostaticsShihhsien S. Kuo, Michael D. Altman, Jaydeep P. Bardhan, Bruce Tidor, Jacob K. White. 466-473 [doi]
- Efficient mixed-domain analysis of electrostatic MEMSGang Li, Narayan R. Aluru. 474-477 [doi]
- FastMag: a 3-D magnetostatic inductance extraction program for structures with permeable materialsYehia Massoud, Jacob White. 478-484 [doi]
- Analog circuit sizing based on formal methods using affine arithmeticAndreas C. Lemke, Lars Hedrich, Erich Barke. 486-489 [doi]
- SiSMA: a statistical simulator for mismatch analysis of MOS ICsGiorgio Biagetti, Simone Orcioni, L. Signoracci, Claudio Turchetti, Paolo Crippa, Michele Alessandrini. 490-496 [doi]
- Efficient solution space exploration based on segment trees in analog placement with symmetry constraintsFlorin Balasa, Sarat C. Maruvada, Karthik Krishnamoorthy. 497-502 [doi]
- Post global routing RLC crosstalk budgetingJinjun Xiong, Jun Chen, James Ma, Lei He. 504-509 [doi]
- A technology-independent CAD tool for ESD protection device extraction: ESDExtractorRouying Zhan, Haigang Feng, Qiong Wu, Guang Chen, Xiaokang Guan, Albert Z. Wang. 510-513 [doi]
- On mask layout partitioning for electron projection lithographyRuiqi Tian, Ronggang Yu, Xiaoping Tang, D. F. Wong. 514-518 [doi]
- High capacity and automatic functional extraction tool for industrial VLSI circuit designsSasha Novakovsky, Shy Shyman, Ziyad Hanna. 520-525 [doi]
- Combinational equivalence checking through function transformationHee-Hwan Kwak, In-Ho Moon, James H. Kukula, Thomas R. Shiple. 526-533 [doi]
- GSTE through a case studyJin Yang, Amit Goel. 534-541 [doi]
- Whirlpool PLAs: a regular logic structure and their synthesisFan Mo, Robert K. Brayton. 543-550 [doi]
- Metrics for structural logic synthesisPrabhakar Kudva, Andrew Sullivan, William E. Dougherty. 551-556 [doi]
- Simplification of non-deterministic multi-valued networksAlan Mishchenko, Robert K. Brayton. 557-562 [doi]
- High-level synthesis of distributed logic-memory architecturesChao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. 564-571 [doi]
- An energy-conscious algorithm for memory port allocationPreeti Ranjan Panda, Lakshmikantam Chitturi. 572-576 [doi]
- Energy efficient address assignment through minimized memory row switchingSambuddhi Hettiaratchi, Peter Y. K. Cheung, Thomas J. W. Clarke. 577-581 [doi]
- Refining switching window by time slots for crosstalk noise calculationPinhong Chen, Yuji Kukimoto, Kurt Keutzer. 583-586 [doi]
- Noise propagation and failure criteria for VLSI designsVladimir Zolotov, David Blaauw, Supamas Sirichotiyakul, Murat R. Becer, Chanhee Oh, Rajendran Panda, Amir Grinshpon, Rafi Levy. 587-594 [doi]
- Efficient crosstalk noise modeling using aggressor and tree reductionsLi Ding 0002, David Blaauw, Pinaki Mazumder. 595-600 [doi]
- Bit-level scheduling of heterogeneous behavioural specificationsMaría C. Molina, José M. Mendías, Román Hermida. 602-608 [doi]
- Coupling-aware high-level interconnect synthesis for low powerChun-Gi Lyuh, Taewhan Kim, Ki-Wook Kim. 609-613 [doi]
- Layout-driven resource sharing in high-level synthesisJunhyung Um, Jae-Hoon Kim, Taewhan Kim. 614-618 [doi]
- A delay metric for RC circuits based on the Weibull distributionFrank Liu, Chandramouli V. Kashyap, Charles J. Alpert. 620-624 [doi]
- WTA: waveform-based timing analysis for deep submicron circuitsLarry McMurchie, Carl Sechen. 625-631 [doi]
- General framework for removal of clock network pessimismJindrich Zejda, Paul Frain. 632-639 [doi]
- Synthesis of custom processors based on extensible platformsFei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. 641-648 [doi]
- Efficient instruction encoding for automatic instruction set design of configurable ASIPsJong-eun Lee, Kiyoung Choi, Nikil Dutt. 649-654 [doi]
- Synthesis of customized loop caches for core-based embedded systemsSusan Cotterell, Frank Vahid. 655-662 [doi]
- A hierarchical modeling framework for on-chip communication architecturesXinping Zhu, Sharad Malik. 663-671 [doi]
- A new enhanced SPFD rewiring algorithmJason Cong, Joey Y. Lin, Wangning Long. 672-678 [doi]
- Topologically constrained logic synthesisSubarnarekha Sinha, Alan Mishchenko, Robert K. Brayton. 679-686 [doi]
- Resynthesis of multi-level circuits under tight constraints using symbolic optimizationVictor N. Kravets, Karem A. Sakallah. 687-693 [doi]
- Folding of logic functions and its application to look up table compactionShinji Kimura, Takashi Horiyama, Masaki Nakanishi, Hirotsugu Kajihara. 694-697 [doi]
- Schedulability analysis of multiprocessor real-time applications with stochastic task execution timesSorin Manolache, Petru Eles, Zebo Peng. 699-706 [doi]
- Battery-aware power management based on Markovian decision processesPeng Rong, Massoud Pedram. 707-713 [doi]
- Leakage power modeling and reduction with data retentionWeiping Liao, Joseph M. Basile, Lei He. 714-719 [doi]
- Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloadsSteven M. Martin, Krisztián Flautner, Trevor N. Mudge, David Blaauw. 721-725 [doi]
- A realistic variable voltage scheduling model for real-time applicationsBren Mochocki, Xiaobo Sharon Hu, Gang Quan. 726-731 [doi]
- Frame-based dynamic voltage and frequency scaling for a MPEG decoderKihwan Choi, Karthik Dantu, Wei-Chung Cheng, Massoud Pedram. 732-737 [doi]
- Congestion minimization during placement without estimationBo Hu, Malgorzata Marek-Sadowska. 739-745 [doi]
- Free space management for cut-based placementCharles J. Alpert, Gi-Joon Nam, Paul Villarrubia. 746-751 [doi]
- Incremental placement for layout driven optimizations on FPGAsDeshanand P. Singh, Stephen Dean Brown. 752-759 [doi]
- Robust and passive model order reduction for circuits containing susceptance elementsHui Zheng, Lawrence T. Pileggi. 761-766 [doi]
- Efficient model order reduction via multi-node moment matchingYehea I. Ismail. 767-774 [doi]
- Optimization based passive constrained fittingCarlos P. Coelho, Joel R. Phillips, Luis Miguel Silveira. 775-780 [doi]
- SAT and ATPG: Boolean engines for formal hardware verificationArmin Biere, Wolfgang Kunz. 782-785 [doi]
- ATPG-based logic synthesis: an overviewChih-Wei Jim Chang, Malgorzata Marek-Sadowska. 786-789 [doi]
- The A to Z of SoCsReinaldo A. Bergamaschi, John M. Cohn. 790-798 [doi]