SAT and ATPG: Boolean engines for formal hardware verification

Armin Biere, Wolfgang Kunz. SAT and ATPG: Boolean engines for formal hardware verification. In Lawrence T. Pileggi, Andreas Kuehlmann, editors, Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002, San Jose, California, USA, November 10-14, 2002. pages 782-785, ACM, 2002. [doi]

Abstract

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