SAT and ATPG: Boolean engines for formal hardware verification

Armin Biere, Wolfgang Kunz. SAT and ATPG: Boolean engines for formal hardware verification. In Lawrence T. Pileggi, Andreas Kuehlmann, editors, Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002, San Jose, California, USA, November 10-14, 2002. pages 782-785, ACM, 2002. [doi]

@inproceedings{BiereK02,
  title = {SAT and ATPG: Boolean engines for formal hardware verification},
  author = {Armin Biere and Wolfgang Kunz},
  year = {2002},
  doi = {10.1145/774572.774687},
  url = {http://doi.acm.org/10.1145/774572.774687},
  researchr = {https://researchr.org/publication/BiereK02},
  cites = {0},
  citedby = {0},
  pages = {782-785},
  booktitle = {Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002, San Jose, California, USA, November 10-14, 2002},
  editor = {Lawrence T. Pileggi and Andreas Kuehlmann},
  publisher = {ACM},
  isbn = {0-7803-7607-2},
}