Florentin Dartu - researchr alias

researchr

You are not signed in
Sign in
Sign up

Viewing Publication 1 - 22 from 22

2013

To do or not to do hierarchical timing?Florentin Dartu, Qiuyang Wu. ispd 2013: 180 [doi]

2010

Timed Input Pattern Generation for an Accurate Delay Calculation Under Multiple Input SwitchingSeung Hoon Choi, Kunhyuk Kang, Florentin Dartu, Kaushik Roy. tcad, 29(3):497-502, 2010. [doi]

2006

Algorithms for MIS vector generation and pruningKenneth S. Stevens, Florentin Dartu. iccad 2006: 408-414 [doi]

2005

2004

Statistical gate delay model considering multiple input switchingAseem Agarwal, Florentin Dartu, David Blaauw. dac 2004: 658-663 [doi]

Modeling unbuffered latches for timing analysisChirayu S. Amin, Florentin Dartu, Yehea I. Ismail. iccad 2004: 254-260 [doi]

2003

Weibull Based Analytical Waveform ModelChirayu S. Amin, Florentin Dartu, Yehea I. Ismail. iccad 2003: 161-168 [doi]

2002

TETA: transistor-level waveform evaluation for timing analysisEmrah Acar, Florentin Dartu, Lawrence T. Pileggi. tcad, 21(5):605-616, 2002. [doi]

Timed pattern generation for noise-on-delay calculationSeung Hoon Choi, Kaushik Roy, Florentin Dartu. dac 2002: 870-873 [doi]

1998

TETA: Transistor-Level Engine for Timing AnalysisFlorentin Dartu, Lawrence T. Pileggi. dac 1998: 595-598 [doi]

1997

CMOS Gate Delay Models for General RLC LoadingRavishankar Arunachalam, Florentin Dartu, Lawrence T. Pileggi. iccd 1997: 224-229

Calculating Worst-Case Gate Delays Due to Dominant Capacitance CouplingFlorentin Dartu, Lawrence T. Pileggi. dac 1997: 46-51 [doi]

1996

Performance computation for precharacterized CMOS gates with RC loadsFlorentin Dartu, Noel Menezes, Lawrence T. Pileggi. tcad, 15(5):544-553, 1996. [doi]

RC-Interconnect Macromodels for Timing SimulationFlorentin Dartu, Bogdan Tutuianu, Lawrence T. Pileggi. dac 1996: 544-547 [doi]

An Explicit RC-Circuit Delay Approximation Based on the First Three Moments of the Impulse ResponseBogdan Tutuianu, Florentin Dartu, Lawrence T. Pileggi. dac 1996: 611-616 [doi]

1994

A Gate-Delay Model for high-Speed CMOS CircuitsFlorentin Dartu, Noel Menezes, Jessica Qian, Lawrence T. Pillage. dac 1994: 576-580 [doi]

RC interconnect synthesis-a moment fitting approachNoel Menezes, Satyamurthy Pullela, Florentin Dartu, Lawrence T. Pillage. iccad 1994: 418-425 [doi]

1993

Piecewise Linear Macromodels for Elementary Logic and Fuzzy CircuitsIon Constatin Tesu, Florentin Dartu. iscas 1993: 1718-1721

Sign in or sign up to see more results.

runs on WebDSL