Table of Contents

• EDA: this is serious businessRobert Dahlberg, Kurt Keutzer, R. Bingham, Aart J. de Geus, Walden C. Rhines. 1 [doi]
• Design optimizations for microprocessors at low temperatureArman Vassighi, Ali Keshavarzi, Siva Narendra, Gerhard Schrom, Yibin Ye, Seri Lee, Greg Chrysler, Manoj Sachdev, Vivek De. 2-5 [doi]
• Leakage in nano-scale technologies: mechanisms, impact and design considerationsAmit Agarwal, Chris H. Kim, Saibal Mukhopadhyay, Kaushik Roy. 6-11 [doi]
• System level leakage reduction considering the interdependence of temperature and leakageLei He, Weiping Liao, Mircea R. Stan. 12-17 [doi]
• Reducing clock skew variability via cross linksAnand Rajaram, Jiang Hu, Rabi N. Mahapatra. 18-23 [doi]
• Fast and flexible buffer trees that navigate the physical layout environmentCharles J. Alpert, Milos Hrkic, Jiang Hu, Stephen T. Quay. 24-29 [doi]
• Practical repeater insertion for low power: what repeater library do we need?Xun Liu, Yuantao Peng, Marios C. Papaefthymiou. 30-35 [doi]
• Industrial experience with test generation languages for processor verificationMichael L. Behm, John M. Ludden, Yossi Lichtenstein, Michal Rimon, Michael Vinov. 36-40 [doi]
• Defining coverage views to improve functional coverage analysisSigal Asaf, Eitan Marcus, Avi Ziv. 41-44 [doi]
• Systematic functional coverage metric synthesis from hierarchical temporal event relation graphYoung-Su Kwon, Young-Il Kim, Chong-Min Kyung. 45-48 [doi]
• Probabilistic regression suites for functional verificationShai Fine, Shmuel Ur, Avi Ziv. 49-54 [doi]
• Modular scheduling of guarded atomic actionsDaniel L. Rosenband, Arvind. 55-60 [doi]
• Automatic correct scheduling of control flow intensive behavioral descriptions in formal synthesisKai Kapp, Viktor K. Sabelfeld. 61-66 [doi]
• A timing-driven module-based chip design flowFan Mo, Robert K. Brayton. 67-70 [doi]
• Timing closure through a globally synchronous, timing partitioned design methodologyAnders Edman, Christer Svensson. 71-74 [doi]
• Design and reliability challenges in nanometer technologiesShekhar Borkar, Tanay Karnik, Vivek De. 75 [doi]
• A communication-theoretic design paradigm for reliable SOCsNaresh R. Shanbhag. 76 [doi]
• Reliable communication in systems on chipsGiovanni De Micheli. 77 [doi]
• Designing robust microarchitecturesTodd M. Austin. 78 [doi]
• Hierarchical application aware error detection and recoveryRavishankar K. Iyer. 79 [doi]
• When IC yield missed the target, who is at fault?Andreas J. Strojwas, Michael Campbell, Vassilios Gerousis, Jim Hogan, John Kibarian, Marc Levitt, Walter Ng, Dipu Pramanik, Mark Templeton. 80 [doi]
• Memory access scheduling and binding considering energy minimization in multi-bank memory systemsChun-Gi Lyuh, Taewhan Kim. 81-86 [doi]
• Profile-based optimal intra-task voltage scheduling for hard real-time applicationsJaewon Seo, Taewhan Kim, Ki-Seok Chung. 87-92 [doi]
• Requirement-based design methods for adaptive communications linksJuan Antonio Carballo, Kevin J. Nowka, Seung-Moon Yoo, Ivan Vo, Clay Cranford, V. Robert Norman. 93-98 [doi]
• Automated energy/performance macromodeling of embedded softwareAnish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha. 99-102 [doi]
• Coding for system-on-chip networks: a unified frameworkSrinivasa R. Sridhara, Naresh R. Shanbhag. 103-106 [doi]
• Abstraction of assembler programs for symbolic worst case execution time analysisTobias Schüle, Klaus Schneider. 107-112 [doi]
• Extending the transaction level modeling approach for fast communication architecture explorationSudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane. 113-118 [doi]
• Specific scheduling support to minimize the reconfiguration overhead of dynamically reconfigurable hardwareJavier Resano, Daniel Mozos. 119-124 [doi]
• LODS: locality-oriented dynamic scheduling for on-chip multiprocessorsMahmut T. Kandemir. 125-128 [doi]
• An area estimation methodology for FPGA based designs at systemc-levelCarlo Brandolese, William Fornaciari, Fabio Salice. 129-132 [doi]
• Automated design of operational transconductance amplifiers using reversed geometric programmingJohan P. Vanderhaegen, Robert W. Brodersen. 133-138 [doi]
• Correct-by-construction layout-centric retargeting of large analog designsSambuddha Bhattacharya, Nuttorn Jangkrajarng, Roy Hartono, C.-J. Richard Shi. 139-144 [doi]
• Fast and accurate parasitic capacitance models for layout-awareAnuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri. 145-150 [doi]
• ORACLE: optimization with recourse of analog circuits including layout extractionYang Xu, Lawrence T. Pileggi, Stephen P. Boyd. 151-154 [doi]
• A synthesis flow toward fast parasitic closure for radio-frequency integrated circuitsGang Zhang, E. Aykut Dengi, Ronald A. Rohrer, Rob A. Rutenbar, L. Richard Carley. 155-158 [doi]
• Buffer sizing for clock power minimization subject to general skew constraintsKai Wang, Malgorzata Marek-Sadowska. 159-164 [doi]
• Optimal placement of power supply pads and pinsMin Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda. 165-170 [doi]
• A stochastic approach To power grid analysisSanjay Pant, David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda. 171-176 [doi]
• Efficient power/ground network analysis for power integrity-driven design methodologySu-Wei Wu, Yao-Wen Chang. 177-180 [doi]
• Reliability-driven layout decompaction for electromigration failure avoidance in complex mixed-signal IC designsGoeran Jerke, Jens Lienig, Jürgen Scheible. 181-184 [doi]
• What happened to ASIC?: Go (recon)figure?Nitin Deo, Behrooz Zahiri, Ivo Bolsens, Jason Cong, Bhusan Gupta, Philip Lopresti, Christopher B. Reynolds, Chris Rowen, Ray Simar. 185 [doi]
• Optical proximity correction (OPC): friendly maze routingLi-Da Huang, Martin D. F. Wong. 186-191 [doi]
• Design automation for mask programmable fabricsNarendra V. Shenoy, Jamil Kawa, Raul Camposano. 192-197 [doi]
• On designing via-configurable cell blocks for regular fabricsYajun Ran, Malgorzata Marek-Sadowska. 198-203 [doi]
• Routing architecture exploration for regular fabricsV. Kheterpal, Andrzej J. Strojwas, Lawrence T. Pileggi. 204-207 [doi]
• Accurate pre-layout estimation of standard cell characteristicsHiroaki Yoshida, Kaushik De, Vamsi Boppana. 208-211 [doi]
• An efficient finite-domain constraint solver for circuitsGanapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang. 212-217 [doi]
• Automatic abstraction and verification of verilog modelsZaher S. Andraus, Karem A. Sakallah. 218-223 [doi]
• Abstraction refinement by controllability and cooperativeness analysisFreddy Y. C. Mang, Pei-Hsin Ho. 224-229 [doi]
• Verifying a gigabit ethernet switch using SMVYuan Lu, Mike Jorda. 230-233 [doi]
• A general decomposition strategy for verifying register renamingHazem I. Shehata, Mark Aagaard. 234-237 [doi]
• An integrated hardware/software approach for run-time scratchpad managementFrancesco Poletti, Paul Marchal, David Atienza, Luca Benini, Francky Catthoor, Jose Manuel Mendias. 238-243 [doi]
• Multi-profile based code compressionEduardo Wanderley Netto, Rodolfo Azevedo, Paulo Centoducatte, Guido Araujo. 244-249 [doi]
• An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memorySang-Il Han, Amer Baghdadi, Marius Bonaciu, Soo-Ik Chae, Ahmed Amine Jerraya. 250-255 [doi]
• Operating-system controlled network on chipVincent Nollet, Théodore Marescaux, Diederik Verkest, Jean-Yves Mignolet, Serge Vernalde. 256-259 [doi]
• DyAD: smart routing for networks-on-chipJingcao Hu, Radu Marculescu. 260-263 [doi]
• Business models in IP, software licensing, and servicesEllen Sentovich, Raul Camposano, Jim Douglas, Aurangzeb Khan. 264 [doi]
• Competitive strategies for the electronics industryEllen Sentovich, Jaswinder Ahuja, Paul Lippe, Bernie Rosenthal. 264 [doi]
• Timing closure for low-FO4 microprocessor designDavid S. Kung. 265-266 [doi]
• Forest vs. trees: where s the slack?Paul K. Rodman. 267 [doi]
• Efficient timing closure without timing driven placement and routingMiodrag Vujkovic, David Wadkins, William Swartz, Carl Sechen. 268-273 [doi]
• Verification: what works and what doesn tFrancine Bacchini, Robert F. Damiano, Bob Bentley, Kurt Baty, Kevin Normoyle, Makoto Ishii, Einat Yogev. 274 [doi]
• Leakage aware dynamic voltage scaling for real-time embedded systemsRavindra Jejurikar, Cristiano Pereira, Rajesh K. Gupta. 275-280 [doi]
• Retargetable profiling for rapid, early system-level design space explorationLukai Cai, Andreas Gerstlauer, Daniel Gajski. 281-286 [doi]
• High level cache simulation for heterogeneous multiprocessorsJoshua J. Pieper, Alain Mellan, JoAnn M. Paul, Donald E. Thomas, Faraydon Karim. 287-292 [doi]
• Communication-efficient hardware acceleration for fast functional simulationYoung-Il Kim, Woo-Seung Yang, Young-Su Kwon, Chong-Min Kyung. 293-298 [doi]
• A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communicationYuichi Nakamura, Kohei Hosokawa, Ichiro Kuroda, Ko Yoshikawa, Takeshi Yoshimura. 299-304 [doi]
• Circuit-aware architectural simulationSeokwoo Lee, Shidhartha Das, Valeria Bertacco, Todd M. Austin, David Blaauw, Trevor N. Mudge. 305-310 [doi]
• Toward a methodology for manufacturability-driven design rule explorationLuigi Capodieci, Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang. 311-316 [doi]
• Phase correct routing for alternating phase shift masksKevin W. McCullen. 317-320 [doi]
• Toward a systematic-variation aware timing methodologyPuneet Gupta, Fook-Luen Heng. 321-326 [doi]
• Selective gate-length biasing for cost-effective runtime leakage controlPuneet Gupta, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester. 327-330 [doi]
• First-order incremental block-based statistical timing analysisChandramouli Visweswariah, K. Ravindran, K. Kalafala, Steven G. Walker, S. Narayan. 331-336 [doi]
• Fast statistical timing analysis handling arbitrary delay correlationsMichael Orshansky, Arnab Bandyopadhyay. 337-342 [doi]
• STAC: statistical timing analysis with correlationJiayong Le, Xin Li, Lawrence T. Pileggi. 343-348 [doi]
• System level design: six success stories in search of an industryFrancine Bacchini, Pierre G. Paulin, Reinaldo A. Bergamaschi, Raj Pawate, Arie Bernstein, Ramesh Chandra, Mohamed Ben-Romdhane. 349-350 [doi]
• Large-scale placement by grid-warpingZhong Xiu, James D. Z. Ma, Suzanne M. Fowler, Rob A. Rutenbar. 351-356 [doi]
• Placement feedback: a concept and method for better min-cut placementsAndrew B. Kahng, Sherief Reda. 357-362 [doi]
• Quantum-Dot Cellular Automata (QCA) circuit partitioning: problem modeling and solutionsDominic A. Antonelli, Danny Z. Chen, Timothy J. Dysart, Xiaobo Sharon Hu, Andrew B. Kahng, Peter M. Kogge, Richard C. Murphy, Michael T. Niemier. 363-368 [doi]
• Passivity-preserving model reduction via a computationally efficient project-and-balance schemeNgai Wong, Venkataramanan Balakrishnan, Cheng-Kok Koh. 369-374 [doi]
• A linear fractional transform (LFT) based model for interconnect parametric uncertaintyJanet Meiling Wang, Omar Hafiz, Jun Li. 375-380 [doi]
• Variational delay metrics for interconnect timing analysisKanak Agarwal, Dennis Sylvester, David Blaauw, Frank Liu, Sani R. Nassif, Sarma B. K. Vrudhula. 381-384 [doi]
• Exploiting input information in a model reduction algorithm for massively coupled parasitic networksLuis Miguel Silveira, Joel R. Phillips. 385-388 [doi]
• Automatic translation of software binaries onto FPGAsGaurav Mittal, David Zaretsky, Xiaoyong Tang, Prithviraj Banerjee. 389-394 [doi]
• Area-efficient instruction set synthesis for reconfigurable system-on-chip designsPhilip Brisk, Adam Kaplan, Majid Sarrafzadeh. 395-400 [doi]
• Data compression for improving SPM behaviorOzcan Ozturk, Mahmut T. Kandemir, I. Demirkiran, Guangyu Chen, Mary Jane Irwin. 401-406 [doi]
• Platform based design: does it answer the entire SoC challenge?Gary Smith. 407 [doi]
• Nomadic platform approach for wireless mobile multimediaMark Hopkins. 408 [doi]
• Benefits and challenges for platform-based designAlberto L. Sangiovanni-Vincentelli, Luca P. Carloni, Fernando De Bernardinis, Marco Sgroi. 409-414 [doi]
• Trends in the use of re-configurable platformsMax Baron. 415 [doi]
• A recursive paradigm to solve Boolean relationsDavid Bañeres, Jordi Cortadella, Michael Kishinevsky. 416-421 [doi]
• A robust algorithm for approximate compatible observability don t care (CODC) computationNikhil Saluja, Sunil P. Khatri. 422-427 [doi]
• A method to decompose multiple-output logic functionsTsutomu Sasao, Munehiro Matsuura. 428-433 [doi]
• Symmetry detection for incompletely specified functionsKuo-Hua Wang, Jia-Hung Chen. 434-437 [doi]
• Implicit enumeration of structural changes in circuit optimizationVictor N. Kravets, Prabhakar Kudva. 438-441 [doi]
• Parametric yield estimation considering leakage variabilityRajeev R. Rao, Anirudh Devgan, David Blaauw, Dennis Sylvester. 442-447 [doi]
• A methodology to improve timing yield in the presence of process variationsSreeja Raj, Sarma B. K. Vrudhula, Janet Meiling Wang. 448-453 [doi]
• Novel sizing algorithm for yield improvement under process variation in nanometer technologySeung Hoon Choi, Bipul Chandra Paul, Kaushik Roy. 454-459 [doi]
• Statistical timing analysis based on a timing yield modelFarid N. Najm, Noel Menezes. 460-465 [doi]
• System design for DSP applications in transaction level modeling paradigmAbhijit K. Deb, Axel Jantsch, Johnny Öberg. 466-471 [doi]
• An analytical approach for dynamic range estimationBin Wu, Jianwen Zhu, Farid N. Najm. 472-477 [doi]
• Automated fixed-point data-type optimization tool for signal processing and communication systemsChangchun Shi, Robert W. Brodersen. 478-483 [doi]
• An algorithm for converting floating-point computations to fixed-point in MATLAB based FPGA designSanghamitra Roy, Prithviraj Banerjee. 484-487 [doi]
• Synthesizing interconnect-efficient low density parity check codesMarghoob Mohiyuddin, Amit Prakash, Adnan Aziz, Wayne Wolf. 488-491 [doi]
• On path-based learning and its applications in delay test and diagnosisLi-C. Wang, T. M. Mak, Kwang-Ting Cheng, Magdy S. Abadir. 492-497 [doi]
• Efficient on-line testing of FPGAs with provable diagnosabilitiesVinay Verma, Shantanu Dutt, Vishal Suthar. 498-503 [doi]
• Is statistical timing statistically significant?Richard Goldman, Kurt Keutzer, Clive Bittlestone, Ahsan Bootehsaz, Shekhar Y. Borkar, E. Chen, Louis Scheffer, Chandramouli Visweswariah. 498 [doi]
• On test generation for transition faults with minimized peak power dissipationWei Li, Sudhakar M. Reddy, Irith Pomeranz. 504-509 [doi]
• A new state assignment technique for testing and low powerSungju Park, Sangwook Cho, Seiyang Yang, Maciej J. Ciesielski. 510-513 [doi]
• Automatic generation of breakpoint hardware for silicon debugBart Vermeulen, Mohammad Zalfany Urfianto, Sandeep Kumar Goel. 514-517 [doi]
• AMUSE: a minimally-unsatisfiable subformula extractorYoonna Oh, Maher N. Mneimneh, Zaher S. Andraus, Karem A. Sakallah, Igor L. Markov. 518-523 [doi]
• A SAT-based algorithm for reparameterization in symbolic simulationPankaj Chauhan, Edmund M. Clarke, Daniel Kroening. 524-529 [doi]
• Exploiting structure in symmetry detection for CNFPaul T. Darga, Mark H. Liffiton, Karem A. Sakallah, Igor L. Markov. 530-534 [doi]
• Refining the SAT decision ordering for bounded model checkingChao Wang, HoonSang Jin, Gary D. Hachtel, Fabio Somenzi. 535-538 [doi]
• Efficient equivalence checking with partitions and hierarchical cut-pointsDemos Anastasakis, Lisa McIlwain, Slawomir Pilarski. 539-542 [doi]
• Were the good old days all that good?: EDA then and nowShishpal Rawat, William H. Joyner Jr., John A. Darringer, Daniel Gajski, Pat O. Pistilli, Hugo De Man, Carl Harris, James Solomon. 543 [doi]
• Off-chip latency-driven dynamic voltage and frequency scaling for an MPEG decodingKihwan Choi, Ramakrishna Soma, Massoud Pedram. 544-549 [doi]
• Energy-aware deterministic fault tolerance in distributed real-time embedded systemsYing Zhang, Robert P. Dick, Krishnendu Chakrabarty. 550-555 [doi]
• Proxy-based task partitioning of watermarking algorithms for reducing energy consumption in mobile devicesArun Kejariwal, Sumit Gupta, Alexandru Nicolau, Nikil Dutt, Rajesh Gupta. 556-561 [doi]
• Adaptive data partitioning for ambient multimediaXiaoping Hu, Radu Marculescu. 562-565 [doi]
• Energy characterization of filesystems for diskless embedded systemsSiddharth Choudhuri, Rabi N. Mahapatra. 566-569 [doi]
• A method for correcting the functionality of a wire-pipelined circuitVidyasagar Nookala, Sachin S. Sapatnekar. 570-575 [doi]
• A new approach to latency insensitive designMario R. Casu, Luca Macchiarulo. 576-581 [doi]
• Pre-layout wire length and congestion estimationQinghua Liu, Malgorzata Marek-Sadowska. 582-587 [doi]
• The best of both worlds: the efficient asynchronous implementation of synchronous specificationsAbhijit Davare, Kelvin Lwin, Alex Kondratyev, Alberto L. Sangiovanni-Vincentelli. 588-591 [doi]
• Fast hazard detection in combinational circuitsCheoljoo Jeong, Steven M. Nowick. 592-595 [doi]
• Defect tolerant probabilistic design paradigm for nanotechnologiesMargarida F. Jacome, Chen He, Gustavo de Veciana, Stephen Bijansky. 596-601 [doi]
• Architecture-level synthesis for automatic interconnect pipeliningJason Cong, Yiping Fan, Zhiru Zhang. 602-607 [doi]
• Automatic generation of equivalent architecture model from functional specificationSamar Abdi, Daniel Gajski. 608-613 [doi]
• Divide-and-concatenate: an architecture level optimization technique for universal hash functionsBo Yang, Ramesh Karri, David A. McGrew. 614-617 [doi]
• Performance analysis of different arbitration algorithms of the AMBA AHB busMassimo Conti, Marco Caldari, Giovanni B. Vece, Simone Orcioni, Claudio Turchetti. 618-621 [doi]
• Design tools for BioMEMSTom Korsmeyer, Jun Zeng, Ken Greiner. 622-628 [doi]
• CAD challenges in BioMEMS designJacob White. 629-632 [doi]
• Will Moore s Law rule in the land of analog?Rob A. Rutenbar, Anthony R. Bonaccio, Teresa H. Y. Meng, Ernesto Perea, Robert Pitts, Charles Sodini, Jim Wieser. 633 [doi]
• Profile-guided microarchitectural floorplanning for deep submicron processor designMongkol Ekpanyapong, Jacob R. Minz, Thaisiri Watewai, Hsien-Hsin S. Lee, Sung Kyu Lim. 634-639 [doi]
• Floorplanning optimization with trajectory piecewise-linear model for pipelined interconnectsChangbo Long, Lucanus J. Simonson, Weiping Liao, Lei He. 640-645 [doi]
• A packing algorithm for non-manhattan hexagon/triangle placement design by using an adaptive o-tree representationJing Li, Tan Yan, Bo Yang, Juebang Yu, Chunhui Li. 646-651 [doi]
• Worst-case circuit delay taking into account power supply variationsDionysios Kouroussis, Rubil Ahmadi, Farid N. Najm. 652-657 [doi]
• Statistical gate delay model considering multiple input switchingAseem Agarwal, Florentin Dartu, David Blaauw. 658-663 [doi]
• Static timing analysis using backward signal propagationDongwoo Lee, Vladimir Zolotov, David Blaauw. 664-669 [doi]
• Design and implementation of the POWER5 microprocessorJoachim G. Clabes, Joshua Friedrich, Mark Sweet, Jack DiLullo, Sam Chu, Donald W. Plass, James Dawson, Paul Muench, Larry Powell, Michael S. Floyd, Balaram Sinharoy, Mike Lee, Michael Goulet, James Wagoner, Nicole S. Schwartz, Stephen L. Runyon, Gary Gorman, Phillip Restle, Ronald N. Kalla, Joseph McGill, Steve Dodson. 670-672 [doi]
• A dual-core 64b ultraSPARC microprocessor for dense server applicationsToshinari Takayanagi, Jinuk Luke Shin, Bruce Petrick, Jeffrey Su, Ana Sonia Leon. 673-677 [doi]
• Low voltage swing logic circuits for a Pentium 4 processor integer coreDaniel J. Deleganes, Micah Barany, George Geannopoulos, Kurt Kreitzer, Anant P. Singh, Sapumal Wijeratne. 678-680 [doi]
• The future of multiprocessor systems-on-chipsWayne Wolf. 681-685 [doi]
• Heterogeneous MP-SoC: the solution to energy-efficient signal processingTim Kogel, Heinrich Meyr. 686-691 [doi]
• Flexible architectures for engineering successful SOCsChris Rowen, Steve Leibson. 692-697 [doi]
• Modeling repeaters explicitly within analytical placementPrashant Saxena, Bill Halpin. 699-704 [doi]
• Quadratic placement using an improved timing modelBernd Obermeier, Frank M. Johannes. 705-710 [doi]
• An approach to placement-coupled logic replicationMilos Hrkic, John Lillis, Giancarlo Beraudo. 711-716 [doi]
• A novel approach for flexible and consistent ADL-driven ASIP designGunnar Braun, Achim Nohl, Weihua Sheng, Jianjiang Ceng, Manuel Hohenauer, Hanno Scharwächter, Rainer Leupers, Heinrich Meyr. 717-722 [doi]
• Characterizing embedded applications for instruction-set extensible processorsPan Yu, Tulika Mitra. 723-728 [doi]
• Introduction of local memory elements in instruction set extensionsPartha Biswas, Vinay Choudhary, Kubilay Atasu, Laura Pozzi, Paolo Ienne, Nikil Dutt. 729-734 [doi]
• FPGA power reduction using configurable dual-VddFei Li, Yan Lin, Lei He. 735-740 [doi]
• Multi-resource aware partitioning algorithms for FPGAs with heterogeneous resourcesNavaratnasothie Selvakkumaran, Abhishek Ranjan, Salil Raje, George Karypis. 741-746 [doi]
• An SoC design methodology using FPGAs and embedded microprocessorsNobuyuki Ohba, Kohji Takano. 747-752 [doi]
• Security as a new dimension in embedded system designSrivaths Ravi, Paul C. Kocher, Ruby B. Lee, Gary McGraw, Anand Raghunathan. 753-760 [doi]
• Tradeoffs between date oxide leakage and delay for dual T::ox:: circuitsAnup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar. 761-766 [doi]
• Implicit pseudo boolean enumeration algorithms for input vector controlKaviraj Chopra, Sarma B. K. Vrudhula. 767-772 [doi]
• Statistical optimization of leakage power considering process variations using dual-Vth and sizingAshish Srivastava, Dennis Sylvester, David Blaauw. 773-778 [doi]
• Leakage-and crosstalk-aware bus encoding for total power reductionHarmander Deogun, Rajeev R. Rao, Dennis Sylvester, David Blaauw. 779-782 [doi]
• Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignmentAshish Srivastava, Dennis Sylvester, David Blaauw. 783-787 [doi]
• Sparse transformations and preconditioners for hierarchical 3-D capacitance extraction with multiple dielectricsShu Yan, Vivek Sarin, Weiping Shi. 788-793 [doi]
• A fast parasitic extractor based on low-rank multilevel matrix compression for conductor and dielectric modeling in microelectronics and MEMSDipanjan Gope, Swagato Chakraborty, Vikram Jandhyala. 794-799 [doi]
• CHIME: coupled hierarchical inductance model evaluationSatrajit Gupta, Lawrence T. Pileggi. 800-805 [doi]
• Large-scale full-wave simulationSharad Kapur, David E. Long. 806-809 [doi]
• Closed-form expressions of distributed RLC interconnects for analysis of on-chip inductance effectsYuichi Tanji, Hideki Asai. 810-813 [doi]
• Re-synthesis for delay variation toleranceShih-Chieh Chang, Cheng-Tao Hsieh, Kai-Chiang Wu. 814-819 [doi]
• Post-layout logic optimization of domino circuitsAiqun Cao, Cheng-Kok Koh. 820-825 [doi]
• Multiple constant multiplication by time-multiplexed mapping of addition chainsPeter Tummeltshammer, James C. Hoe, Markus Püschel. 826-829 [doi]
• Decomposing specifications with concurrent outputs to resolve state coding conflicts in asynchronous logic synthesisHemangee K. Kapoor, Mark B. Josephs. 830-833 [doi]
• A new heuristic algorithm for reversible logic synthesisPawel Kerntopf. 834-837 [doi]
• Quantum logic synthesis by symbolic reachability analysisWilliam N. N. Hung, Xiaoyu Song, Guowu Yang, Jin Yang, Marek A. Perkowski. 838-841 [doi]
• A frequency relaxation approach for analog/RF system-level simulationXin Li, Yang Xu, Peng Li, Padmini Gopalakrishnan, Lawrence T. Pileggi. 842-847 [doi]
• Robust, stable time-domain methods for solving MPDEs of fast/slow systemsTing Mei, Jaijeet S. Roychowdhury, Todd S. Coffey, Scott A. Hutchinson, David M. Day. 848-853 [doi]
• High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effectsGeert Van der Plas, Mustafa Badaroglu, Gerd Vandersteen, Petr Dobrovolný, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man. 854-859 [doi]
• Hierarchical approach to exact symbolic analysis of large analog circuitsSheldon X.-D. Tan, Weikun Guo, Zhenyu Qi. 860-863 [doi]
• An Essentially Non-Oscillatory (ENO) high-order accurate Adaptive table model for device modelingBaolin Yang, Bruce McGaughy. 864-867 [doi]
• Theoretical and practical limits of dynamic voltage scalingBo Zhai, David Blaauw, Dennis Sylvester, Krisztián Flautner. 868-873 [doi]
• Enabling energy efficiency in via-patterned gate array devicesR. Reed Taylor, Herman Schmit. 874-878 [doi]
• Compact thermal modeling for temperature-aware designWei Huang, Mircea R. Stan, Kevin Skadron, Karthik Sankaranarayanan, Shougata Ghosh, Sivakumar Velusamy. 878-883 [doi]
• Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant eraAnirban Basu, Sheng-Chih Lin, Vineet Wason, Amit Mehrotra, Kaustav Banerjee. 884-887 [doi]
• Noise characterization of static CMOS gatesRouwaida Kanj, Timothy Lehner, Bhavna Agrawal, Elyse Rosenbaum. 888-893 [doi]
• A scalable soft spot analysis methodology for compound noise effects in nano-meter circuitsChong Zhao, Xiaoliang Bai, Sujit Dey. 894-899 [doi]
• A novel technique to improve noise immunity of CMOS dynamic logic circuitsLi Ding 0002, Pinaki Mazumder. 900-903 [doi]
• Statistical timing analysis in sequential circuit for on-chip global interconnect pipeliningLizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen. 904-907 [doi]
• Debugging HW/SW interface for MPSoC: video encoder system design case studyMohamed-Wassim Youssef, Sungjoo Yoo, Arif Sasongko, Yanick Paviot, Ahmed Amine Jerraya. 908-913 [doi]
• SUNMAP: a tool for automatic topology selection and generation for NoCsSrinivasan Murali, Giovanni De Micheli. 914-919 [doi]
• FITS: framework-based instruction-set tuning synthesis for embedded application specific processorsAllen C. Cheng, Gary S. Tyson, Trevor N. Mudge. 920-923 [doi]
• Mapping a domain specific language to a platform FPGAChidamber Kulkarni, Gordon J. Brebner, Graham Schelle. 924-927 [doi]
• On the generation of scan-based test sets with reachable states for testing under functional operation conditionsIrith Pomeranz. 928-933 [doi]
• Scalable selector architecture for x-tolerant deterministic BISTPeter Wohl, John A. Waicukauski, Sanjay Patel. 934-939 [doi]
• Scan-BIST based on transition probabilitiesIrith Pomeranz. 940-943 [doi]
• Combining dictionary coding and LFSR reseeding for test data compressionXiaoyun Sun, Larry L. Kinney, Bapiraju Vinnakota. 944-947 [doi]
• Virtual memory window for application-specific reconfigurable coprocessorsMiljan Vuletic, Laura Pozzi, Paolo Ienne. 948-953 [doi]
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