Bapiraju Vinnakota - researchr alias

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Viewing Publication 1 - 59 from 59

2022

SCIP to the Next Generation of Computing: Extending More than Moore with Silicon Photonics Chiplets in Package (SCIP)Vivek Raghunathan, Karl Muth, Bapiraju Vinnakota, Prasad Venugopal, Rebecca Schaevitz, Manish Mehta. isqed 2022: 1-6 [doi]

2021

2020

2019

A Bunch of Wires (BoW) Interface for Inter-Chiplet CommunicationRamin Farjadrad, Bapiraju Vinnakota. hoti 2019: 27-273 [doi]

High Capacity On-Package Physical Link ConsiderationsGreg Taylor, Ramin Farjadrad, Bapiraju Vinnakota. hoti 2019: 19-22 [doi]

2004

A digital DFT technique for verifying the static performance of A/D convertersWooyoung Choi, Bapiraju Vinnakota, Ramesh Harjani. cicc 2004: 207-210 [doi]

Combining dictionary coding and LFSR reseeding for test data compressionXiaoyun Sun, Larry L. Kinney, Bapiraju Vinnakota. dac 2004: 944-947 [doi]

2003

Test Vector Generation Based on Correlation Model for Ratio-IddqXiaoyun Sun, Larry L. Kinney, Bapiraju Vinnakota. itc 2003: 545-554 [doi]

Development of Energy Consumption Ratio TestXiaoyun Sun, Larry L. Kinney, Bapiraju Vinnakota. vts 2003: 279-286 [doi]

2002

Statistical threshold formulation for dynamic I::dd:: testWanli Jiang, Bapiraju Vinnakota. tcad, 21(6):694-705, 2002. [doi]

2001

2000

1999

1998

Fast State VerificationDechang Sun, Bapiraju Vinnakota, Wanli Jiang. dac 1998: 619-624 [doi]

Fast fault translationBapiraju Vinnakota, Jason Andrews. tvlsi, 6(1):122-133, 1998. [doi]

Process-tolerant test with energy consumption ratioBapiraju Vinnakota, Wanli Jiang, Dechang Sun. itc 1998: 1027-1036 [doi]

1997

Workload Distribution in Fault SimulationMinesh B. Amin, Bapiraju Vinnakota. et, 10(3):277-282, 1997. [doi]

Monitoring Power Dissipation for Fault DetectionBapiraju Vinnakota. et, 11(2):173-181, 1997. [doi]

Pseudoduplication - An ACOB Technique for Single-Ended CircuitsBapiraju Vinnakota, Ramesh Harjani, Wooyoung Choi. vlsid 1997: 398-402 [doi]

1996

Zamlog: a parallel algorithm for fault simulation based on ZambeziMinesh B. Amin, Bapiraju Vinnakota. iccad 1996: 509-512 [doi]

ZAMBEZI: a parallel pattern parallel fault sequential circuit fault simulatorMinesh B. Amin, Bapiraju Vinnakota. vts 1996: 438-443 [doi]

Monitoring power dissipation for fault detectionBapiraju Vinnakota. vts 1996: 483-488 [doi]

Mixed-Signal Design for TestBapiraju Vinnakota, Ramesh Harjani. vlsid 1996: 2 [doi]

1995

Data parallel fault simulationMinesh B. Amin, Bapiraju Vinnakota. iccd 1995: 610-615 [doi]

Implementing Multiplication with Split Read-Only MemoryBapiraju Vinnakota. TC, 44(11):1352-1356, 1995.

Reducing test application time in scan design schemesBapiraju Vinnakota, Nicholas J. Stessman. vts 1995: 367-373 [doi]

System-Level Design for Test of Fully Differential Analog CircuitsBapiraju Vinnakota, Ramesh Harjani, Nicholas J. Stessman. dac 1995: 450-454 [doi]

1994

1993

A C-Testable Carry-Free DividerHosahalli R. Srinivas, Bapiraju Vinnakota, Keshab K. Parhi. iccd 1993: 206-213

Synthesis of Algorithm-Based Fault-Tolerant Systems from Dependence GraphsBapiraju Vinnakota, Niraj K. Jha. tpds, 4(8):864-874, 1993. [doi]

Diagnosability and Diagnosis of Algorithm-Based Fault-Tolerant SystemsBapiraju Vinnakota, Niraj K. Jha. TC, 42(8):924-937, 1993.

1992

Repair of RAMs With Clustered FaultsBapiraju Vinnakota, Jason Andrews. iccd 1992: 582-585

1991

MACHETE: synthesis of sequential machines for easy testabilityBapiraju Vinnakota, Niraj K. Jha. eurodac 1991: 289-293 [doi]

Design of Multiprocessor Systems for Concurrent Error Detection and Fault DiagnosisBapiraju Vinnakota, Niraj K. Jha. ftcs 1991: 504-511

1990

A dependence graph-based approach to the design of algorithm-based fault tolerant systemsBapiraju Vinnakota, Niraj K. Jha. ftcs 1990: 122-129 [doi]

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