Table of Contents

• Exploiting defect clustering to screen bare die for infant mortality failures: an experimental studyDavid R. Lakin II, Adit D. Singh. 23-30
• A probe scheduling algorithm for MCM substratesBruce C. Kim, Pinshan Jiang, Se Hyun Park. 31-37
• Testing an MCM for high-energy physics experiments: a case studyAlfredo Benso, Silvia Chiusano, Paolo Prinetto, Simone Giovannetti, Riccardo Mariani, Silvano Motto. 38-46
• Transient current testing of 0.25 /spl mu/m CMOS devicesBram Kruseman, Peter Janssen, Victor Zieren. 47-56
• Statistical threshold formulation for dynamic I_dd testWanli Jiang, Bapiraju Vinnakota. 57-66
• Defect detection using power supply transient signal analysisAmy Germida, Zheng Yan, James F. Plusquellic, Fidel Muradali. 67-76
• Minimized power consumption for scan-based BISTStefan Gerstendörfer, Hans-Joachim Wunderlich. 77-84
• LT-RTPG: a new test-per-scan BIST TPG for low heat dissipationSeongmoon Wang, Sandeep K. Gupta. 85-94
• Fault diagnosis in scan-based BIST using both time and space informationJayabrata Ghosh-Dastidar, Debaleena Das, Nur A. Touba. 95-102
• Expediting ramp-to-volume productionHari Balachandran, Jason Parker, Gordon Gammie, John W. Olson, Craig Force, Kenneth M. Butler, Sri Jandhyala. 103-112
• Applications of semiconductor test economics, and multisite testing to lower cost of testAndrew C. Evans. 113-123
• Test process optimization: closing the gap in the defect spectrumNorma Barrett, Simon Martin, Chryssa Dislis. 124-129
• The test and debug features of the AMD-K7 microprocessorTimothy J. Wood. 130-136
• DFT advances in the Motorola s MPC7400, a PowerPC G4 microprocessorCarol Pyron, Mike Alexander, James Golab, George Joos, Bruce Long, Robert F. Molyneaux, Rajesh Raina, Nandu Tendolkar. 137-146
• Towards reducing functional only fails for the UltraSPARC microprocessorsAnjali Kinra. 147-154
• Breaking the complexity spiral in board testStehpehn F. Scheiber. 155-158
• The integration of boundary-scan test methods to a mixed-signal environmentAdam W. Ley. 159-162
• Using LSSD to test modules at the board levelThomas A. Ziaja. 163-170
• Switch-level delay testSuriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer. 171-180
• Delay testing considering power supply noise effectsYi-Min Jiang, Angela Krstic, Kwang-Ting Cheng. 181-190
• Test generation for crosstalk-induced delay in integrated circuitsWei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer. 191-200
• Accurate path delay fault coverage is feasibleSpyros Tragoudas. 201-210
• High speed digital transceivers: A challenge for manufacturingClifford B. Cole, Thomas P. Warwick. 211-215
• A new approach to RF impedance testDino Ren Tao. 216-220
• Subband filtering scheme for analog and mixed-signal circuit testingJeongjin Roh, Jacob A. Abraham. 221-229
• Speed-up of high accuracy analog test stimulus optimizationAbdelhakim Khouas, Anne Derieux. 230-236
• Design of a test simulation environment for test program developmentJ. J. O. Riordan. 237-244
• Automatic timing margin failure location analysis by CycleStretch methodMitsuo Matsumoto, Yoshiharu Ikeda. 245-251
• Design for In-System ProgrammingDavid A. Bonnett. 252-259
• Robust testability of primitive faults using test pointsRamesh C. Tekumalla, Premachandran R. Menon. 260-268
• Delay testing of SOI circuits: Challenges with the history effectEric MacDonald, Nur A. Touba. 269-275
• A DFT technique for high performance circuit testingMansour Shashaani, Manoj Sachdev. 276-285
• Testability evaluation of sequential designs incorporating the multi-mode scannable memory elementAdit D. Singh, Egor S. Sogomonyan, Michael Gössel, Markus Seuring. 286-293
• Practical scan test generation and application for embedded FIFOsJeff Rearick. 294-300
• Built-in self-test for GHz embedded SRAMs using flexible pattern generator and new repair algorithmShigeru Nakahara, Keiichi Higeta, Masaki Kohno, Toshiaki Kawamura, Keizo Kakitani. 301-310
• An algorithm for row-column self-repair of RAMs and its implementation in the Alpha 21264Dilip K. Bhavsar. 311-318
• Fault modeling of suspended thermal MEMSBenoît Charlot, Salvador Mir, Érika F. Cota, Marcelo Lubaszewski, Bernard Courtois. 319-328
• Particulate failures for surface-micromachined MEMSTao Jiang, Ronald D. Blanton. 329-337
• IMEMS accelerometer testing-test laboratory development and usageRichard W. Beegle, Robert W. Brocato, Ronald W. Grant. 338-347
• Low overhead test point insertion for scan-based BISTMichinobu Nakao, Seiji Kobayashi, Kazumi Hatayama, Kazuhiko Iijima, Seiji Terada. 348-357
• Logic BIST for large industrial designs: real issues and case studiesGraham Hetherington, Tony Fryars, Nagesh Tamarapalli, Mark Kassab, Abu S. M. Hassan, Janusz Rajski. 358-367
• Synthesis of pattern generators based on cellular automata with phase shiftersGrzegorz Mrugalski, Jerzy Tyszer, Janusz Rajski. 368-377
• Characterization and optimization of the production probing processMinh Quach, Rich Samuelson, David Shaw. 378-387
• RF (gigahertz) ATE production testing on wafer: options and tradeoffsDean A. Gahagan. 388-395
• Probe contact resistance variations during elevated temperature wafer testJerry J. Broz, Reynaldo M. Rincon. 396-405
• Checking sequence generation for asynchronous sequential elementsSezer Gören, F. Joel Ferguson. 406-413
• Functional verification of intellectual properties (IP): a simulation-based solution for an application-specific instruction-set processorManfred Stadler, Thomas Röwer, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner, Markus Thalmann. 414-420
• Critical path identification and delay tests of dynamic circuitsKyung Tek Lee, Jacob A. Abraham. 421-430
• An embedded technique for at-speed interconnect testingBenoit Nadeau-Dostie, Jean-Francois Cote, Harry Hulvershorn, Stephen Pateras. 431-438
• Static component interconnect test technology (SCITT) a new technology for assembly testingAlex Biewenga, Henk D. L. Hollmann, Frans de Jong, Maurice Lousberg. 439-448
• Interconnect delay fault testing with IEEE 1149.1Yuejian Wu, Paul Soong. 449-457
• Correlation of logical failures to a suspect process stepHari Balachandran, Jason Parker, Daniel Shupp, Stephanie Butler, Kenneth M. Butler, Craig Force, Jason Smith. 458-476
• Optimal conditions for Boolean and current detection of floating gate faultsMichel Renovell, André Ivanov, Yves Bertrand, Florence Azaïs, Sumbal Rafiq. 477-486
• Embedded X86 testing methodologyLuis Basto, Asif Khan, Pete Hodakievic. 487-492
• Testing reusable IP-a case studyPeter Harrod. 493-498
• Testing a system-on-a-chip with embedded microprocessorRochit Rajsuman. 499-508
• Towards a standardized procedure for automatic test equipment timing accuracy evaluationY. Cai, W. R. Ortner, C. T. Garrenton. 509-517
• The value of tester accuracyWajih Dalal, Song Miao. 518-523
• An accurate simulation model of the ATE test environment for very high speed devicesThomas P. Warwick, Jung Cho, Yi Cai, Bill Ortner. 524-531
• BIST for phase-locked loops in digital applicationsStephen K. Sunter, Aubin Roy. 532-540
• Auto-calibrating analog timer for on-chip testingB. Provost, E. Sanchez-Sinencio. 541-548
• Effective oscillation-based test for application to a DTMF filter bankGloria Huertas, Diego Vázquez, Adoración Rueda, José L. Huertas. 549-555
• Static component interconnection test technology in practiceFrans de Jong, Rob Raaijmakers. 556-565
• The HASS development processDavid Rahe. 566-576
• Limited access testing of analog circuits: handling tolerancesCherif Ahrikencheikh, Michael Spears. 577-586
• A comparison of bridging fault simulation methodsR. Scott Fetherston, Imtiaz P. Shaik, Siyad C. Ma. 587-595
• Resistive bridge fault modeling, simulation and test generationVijay R. Sar-Dessai, D. M. H. Walker. 596-605
• SymSim: symbolic fault simulation of data-flow data-path designs at the Register-Transfer levelSitaran Yadavalli, Sudhakar M. Reddy. 606-615
• Towards a standard for embedded core test: an exampleYervant Zorian, Erik Jan Marinissen, Rohit Kapur, Tony Taylor, Lee Whetsel. 616-627
• Trends in SLI design and their effect on testRobert C. Aitken, Fidel Muradali. 628-637
• Test features of a core-based co-processor array for video applicationsJos van Beers, Harry Van Herten. 638-647
• Is Analog Fault Simulation a Key to Product Quality? Practical ConsiderationsBozena Kaminska. 648-648
• Analog Fault Simulation: Need it? No. It is already doneEugene R. Atwood. 649
• Analog Fault Simulation: Key to Product Quality, or a Foot in the DoorCraig Force. 650
• Closing The Gap Between Process Development and Mixed Signal Design and TestingHosam Haggag. 651
• Self-checking scheme for very fast clocks skew correctionCecilia Metra, Flavio Giovanelli, Mani Soma, Bruno Riccò. 652-661
• A design diversity metric and reliability analysis for redundant systemsSubhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey. 662-671
• Finite state machine synthesis with concurrent error detectionChaohuang Zeng, Nirmal R. Saxena, Edward J. McCluskey. 672-679
• The evolution of a system test process [for Motorola GSM products]Simon Martin, Robert Bleck, Chryssa Dislis, Des Farren. 680-688
• System design verification tests - an overviewSusana Stoica. 689-697
• PC manufacturing test in a high volume environmentDavid Williams. 698-704
• DFT, test lifecycles and the product lifecycleGordon D. Robinson. 705-713
• An histogram based procedure for current testing of active defectsClaude Thibeault. 714-723
• I/sub DDQ/ testing in deep submicron integrated circuitsAnthony C. Miller. 724-729
• Clustering based techniques for I_DDQ testingSri Jandhyala, Hari Balachandran, Anura P. Jayasumana. 730-737
• Current ratios: a self-scaling technique for production I_DDQ testingPeter C. Maxwell, Pete O Neill, Robert C. Aitken, Ronald Dudley, Neal Jaarsma, Minh Quach, Don Wiseman. 738-746
• Linearity testing issues of analog to digital convertersTurker Kuyel. 747-756
• Estimating the integral non-linearity of A/D-converters via the frequency domainNico Csizmadia, Augustus J. E. M. Janssen. 757-762
• Testing high speed high accuracy analog to digital converters embedded in systems on a chipSolomon Max. 763-771
• Relating linearity test results to design flaws of pipelined analog to digital convertersTurker Kuyel, Haydar Bilhan. 772-779
• Accuracy requirements in at-speed functional testBurnell G. West. 780-787
• A new method for jitter decomposition through its distribution tail fittingMike P. Li, Jan B. Wilstrup, Ross Jessen, Dennis Petrich. 788-794
• At-speed structural testBurnell G. West. 795-800
• Test support processors for enhanced testability of high performance circuitsDavid C. Keezer, Q. Zhou. 801-809
• Design-for-test methodology for Motorola PowerPC microprocessorsMagdy S. Abadir, Rajesh Raina. 810-819
• Testability of the Philips 80C51 micro-controllerM. H. Konijnenburg, J. Th. van der Linden, A. J. van de Goor. 820-829
• Tradeoff analysis for producing high quality tests for custom circuits in PowerPC microprocessorsLi-C. Wang, Magdy S. Abadir. 830-838
• A study of test quality/tester scan memory trade-offs using the SEMATECH test methods dataKenneth M. Butler. 839-847
• Robust test methods applied to functional design verificationSusana Stoica. 848-857
• An integrated approach to behavioral-level design-for-testability using value-range and variable testability techniquesSandhya Seshadri, Michael S. Hsiao. 858-867
• The test requirements model (TeRM) communicating test information throughout the product life cycleLee A. Shombert, Danny C. Davis, Eric M. Bukata. 868-876
• Design for (physical) debug for silicon microsurgery and probing of flip-chip packaged integrated circuitsRichard H. Livengood, Donna Medeiros. 877-882
• The attack of the Holey Shmoos : a case study of advanced DFD and picosecond imaging circuit analysis (PICA)William V. Huott, Moyra K. McManus, Daniel R. Knebel, Steve Steen, Dennis Manzer, Pia Sanda, Steve Wilson, Yuen H. Chan, Antonio Pelella, Stanislav Polonsky. 883-891
• Silicon debug: scan chains alone are not enoughGert-Jan van Rootselaar, Bart Vermeulen. 892-902
• A high-level BIST synthesis method based on a region-wise heuristic for an integer linear programmingHan Bin Kim, Dong Sam Ha. 903-912
• The testability features of the 3rd generation ColdFire family of microprocessorsAlfred L. Crouch, Michael Mateja, Teresa L. McLaurin, John C. Potter, Dat Tran. 913-922
• On achieving complete coverage of delay faults in full scan circuits using locally available linesIrith Pomeranz, Sudhakar M. Reddy. 923-931
• Practical optical waveform probing of flip-chip CMOS devicesKeneth R. Wilsher, William K. Lo. 932-939
• Flexible ATE module with reconfigurable circuit and its application [to CMOS imager test]Tagashi Kitagaki. 940-946
• A method to improve the performance of high-speed waveform digitizingKoji Asami, Shinsuke Tajiri. 947-954
• On-line fault detection in DSP circuits using extrapolated checksums with minimal test pointsSudip Chakrabarti, Abhijit Chatterjee. 955-963
• An efficient on-line-test and back-up scheme for embedded processorsMatthias Pflanz, Heinrich Theodor Vierhaus, F. Pompsch. 964-972
• Using roving STARs for on-line testing and diagnosis of FPGAs in fault-tolerant applicationsMiron Abramovici, Charles E. Stroud, Carter Hamilton, Sajitha Wijesuriya, Vinay Verma. 973-982
• Industrial evaluation of stress combinations for march tests applied to SRAMsA. J. van de Goor, Ivo Schanstra. 983-992
• An on-line BISTed SRAM IP coreMonica Lobetti Bodoni, Alessio Pricco, Alfredo Benso, Silvia Chiusano, Paolo Prinetto. 993-1000
• Port interference faults in two-port memoriesSaid Hamdioui, A. J. van de Goor. 1001-1010
• Using Verilog simulation libraries for ATPGPeter Wohl, John A. Waicukauski. 1011-1020
• STAR-ATPG: a high speed test pattern generator for large scan designsKuo-Hui Tsai, Tompson, Janusz Rajski, Malgorzata Marek-Sadowska. 1021-1030
• Modeling the probability of defect excitation for a commercial IC with implications for stuck-at fault-based ATPG strategiesJennifer Dworak, Michael R. Grimaila, Sooryong Lee, Li-C. Wang, M. Ray Mercer. 1031-1037
• HD-BIST: a hierarchical framework for BIST scheduling and diagnosis in SOCsAlfredo Benso, Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Yervant Zorian. 1038-1044
• Delay fault testing of IP-based designs via symbolic path modelingHyungwon Kim, John P. Hayes. 1045-1054
• Addressable test ports an approach to testing embedded coresLee Whetsel. 1055-1064
• Eliminating the Ouija board: automatic thresholds and probabilistic I_DDQ diagnosisDavid B. Lavo, Tracy Larrabee, Jonathon E. Colburn. 1065-1072
• Diagnostic techniques for the IBM S/390 600 MHz G5 microprocessorPeilin Song, Franco Motika, Daniel R. Knebel, Rick Rizzolo, Mary P. Kusko, Julie Lee, Moyra K. McManus. 1073-1082
• The effects of test compaction on fault diagnosisYun Shao, Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz. 1083-1089
• Is DFT right for you?Jim Johnson. 1090-1097
• Design for test and time to market-friends or foesJon Turino. 1098-1101
• Design for testability: it is time to deliver it for Time-to-MarketBulent Dervisolu. 1102-1111
• High Time For High Level ATPGMahesh A. Iyer. 1112
• High time for high level ATPGWu-Tung Cheng. 1113
• Changing our Path to High Level ATPGScott Davidson. 1114
• High level ATPG is important and is on its way!Rohit Kapur. 1115-1116
• High Time for Higher Level BISTChristos A. Papachristou. 1117
• High-level ATPG: a real topic or an academic amusement?Matteo Sonza Reorda. 1118
• High-level ATPG for Early Power AnalysisWolfgang Roethig. 1119-1120
• SIA Roadmaps: Sunset Boulevard for l_DDQKeith Baker. 1121
• Thin Gate Oxide ReliabilityJeffrey L. Roehr. 1122
• Applying lessons learned from TDDB testingE. James Prendergast. 1123-1124
• ITC 99 Benchmark Circuits - Preliminary ResultsScott Davidson. 1125
• Scan Insertion at the Behavioral LevelChouki Aktouf. 1126
• Benchmarking DAT with the ITC 99 ATPG BenchmarksMario H. Konijnenburg, Hans van der Linden, Jeroen Geuzebroek. 1127
• Application of Tools Developed at the University of Iowa to ITC BenchmarksSudhakar M. Reddy. 1128
• High level test bench generation using software engineering conceptsJean François Santucci, Christophe Paoli. 1129
• Automatic Functional Test Generation - A RealityRaghuram S. Tapuri. 1130
• Panel: Increasing test coverage in a VLSI desgin courseVishwani D. Agrawal. 1131
• Position Statement: Increasing Test Coverage in a VLSI Design CourseJacob A. Abraham. 1132
• Increasing Test Coverage in a VLSI Design CourseMichael L. Bushnell. 1133
• VLSI design 101 - The test moduleJohn Harrington. 1134
• Increasing test coverage in a VLSI design courseMichel Robert. 1135
• Panel Statement: Increasing test coverage in a VLSI design courseMani Soma. 1136
• Position Statement: Testing in a VLSI Design CourseWayne Wolf. 1137
• SCITT: Back to Basics in Mass Production TestingFrans de Jong. 1138
• SCITT: Bringing DRAMs Into the Test FoldFrank W. Angelotti. 1139
• Static Component Interconnection Test Technology (SCITT)Steffen Hellmold. 1140
• DFT is all I can afford, who cares about Design for Yield or Design for Reliability!David M. Wu. 1141-1142
• It Makes Sense to Combine DFT and DFR/DFYRobert C. Aitken. 1143
• DFT, DFY, DFR: Who Cares?R. Scott Fetherston. 1144
• DFT, DFY, and DFR; Which One(s) Do You Worry About?James A. Monzel. 1145
• Design for Yield and Reliability is MORE Important Than DFTD. M. H. Walker. 1146
• DFY and DFR are more important than DFT David M. Wu. 1147
• Output in still, input in stillPeter Wohl. 1148
• STIL: the device-oriented database for the test development lifecycleNathan Biggs. 1149
• Using STIL to describe embedded core test requirementsBrion L. Keller. 1150
• Is there a STIL for mixed signal testing?Marc Loranger. 1151
• Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experimentPhil Nigh, David P. Vallett, Atul Patel, Jason Wright, Franco Motika, Donato Forlenza, Ray Kurtulik, Wendy Chong. 1152-1161