Michinobu Nakao - researchr alias

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Viewing Publication 1 - 10 from 10

2013

Novel Fuse Scheme with a Short Repair Time to Maximize Good Chips per Wafer in Advanced SoCsChizu Matsumoto, Yuichi Hamamura, Michinobu Nakao, Kaname Yamasaki, Yoshikazu Saito, Shun'ichi Kaneko. ieicet, 96-C(1):108-114, 2013. [doi]

2010

Reduction of Area per Good Die for SoC Memory Built-In Self-TestMasayuki Arai, Tatsuro Endo, Kazuhiko Iwasaki, Michinobu Nakao, Iwao Suzuki. ieicet, 93-A(12):2463-2471, 2010. [doi]

2008

Hardware Overhead Reduction for Memory BISTMasayuki Arai, Kazuhiko Iwasaki, Michinobu Nakao, Iwao Suzuki. itc 2008: 1 [doi]

Enhancing Transition Fault Model for Delay Defect DiagnosisWu-Tung Cheng, Brady Benware, Ruifeng Guo, Kun-Han Tsai, Takeo Kobayashi, Kazuyuki Maruo, Michinobu Nakao, Yoshiaki Fukui, Hideyuki Otake. ats 2008: 179-184 [doi]

2002

At-Speed Built-in Test for Logic Circuits with Multiple ClocksKazumi Hatayama, Michinobu Nakao, Yasuo Sato. ats 2002: 292-297 [doi]

Application of High-Quality Built-In Test to Industrial DesignsKazumi Hatayama, Michinobu Nakao, Yoshikazu Kiyoshige, Koichiro Natsume, Yasuo Sato, Takaharu Nagumo. itc 2002: 1003-1012 [doi]

2001

Test Generation for Multiple-Threshold Gate-Delay Fault ModelMichinobu Nakao, Yoshikazu Kiyoshige, Kazumi Hatayama, Yasuo Sato, Takaharu Nagumo. ats 2001: 244 [doi]

1999

Low overhead test point insertion for scan-based BISTMichinobu Nakao, Seiji Kobayashi, Kazumi Hatayama, Kazuhiko Iijima, Seiji Terada. itc 1999: 348-357

1997

Accelerated Test Points Selection Method for Scan-Based BISTMichinobu Nakao, Kazumi Hatayama, Isao Higashi. ats 1997: 359 [doi]

1995

A parallel sequential test generation system DESCARTES based on real-valued logic simulationHiroshi Date, Michinobu Nakao, Kazumi Hatayama. ats 1995: 252-258 [doi]

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