Table of Contents

• Distributed off-line testing of parallel systemsOum-El-Kheir Benkahla, Chouki Aktouf, Chantal Robach. 2-8 [doi]
• An SBus Multi-Tracer and its applicationsH. A. Xie, Kevin E. Forward, K. M. Adams, Suthikshn Kumar. 9-14 [doi]
• Exploitation of parallelism in group probing for testing massively parallel processing systemsYoon-Hwa Choi, Chul Kim. 15-19 [doi]
• A cellular array designed from a Multiple-valued Decision Diagram and its fault testsNaotake Kamiura, Yutaka Hata, Kazuharu Yamato. 20 [doi]
• Boolean process-an analytical approach to circuit representation (II)Yinghua Min, Zhuxing Zhao, Zhongcheng Li. 26-32 [doi]
• Fanout fault analysis for digital logic circuitsJwu E. Chen, Chung-Len Lee, Wen-Zen Shen, Beyin Chen. 33-39 [doi]
• Metastability evaluation method by propagation delay distribution measurementBranka Medved Rogina, Bozidar Vojnovic. 40-44 [doi]
• An approach to hierarchy model checking via evaluating CTL hierarchicallyZuan Zhang. 45 [doi]
• Transistor leakage fault location with ZDDQ measurementXiaoqing Wen, Hideo Tamamoto, Kozo Kinoshita. 51-57 [doi]
• Enhancing multiple fault diagnosis in combinational circuits based on sensitized paths and EB testingHiroshi Takahashi, Nobuhiro Yanagida, Yuzo Takamatsu. 58-64 [doi]
• A simple technique for locating gate-level faults in combinational circuitsTeruhiko Yamada, Koji Yamazaki, Edward J. McCluskey. 65-70 [doi]
• A fault location technique and alternate routing in Benes networkNabanita Das, Jayasree Dattagupta. 71 [doi]
• Overhead reduction techniques for hierarchical fault simulationEiji Harada, Janak H. Patel. 79-85 [doi]
• On the simulation of Multiple Stuck-at Faults using Multiple Domain Concurrent and Comparative SimulationKaren Panetta Lentz, Elias S. Manolakos, Edward C. Czeck. 86-92 [doi]
• Fast fault simulation for BIST applicationsChen-Pin Kung, Chun-Jieh Huang, Chen-Shang Lin. 93-99 [doi]
• Serial transistor network modeling for bridging fault simulationMichel Renovell, P. Huc, Yves Bertrand. 100-106 [doi]
• Hardware-accelerated concurrent fault simulation: eventflow computing versus dataflow computingWinfried Hahn, Andreas Hagerer, R. Kandlbinder. 107 [doi]
• A design-for-test technique for multistage analog circuitsMichel Renovell, Florence Azaïs, Yves Bertrand. 113-119 [doi]
• DC control and observation structures for analog circuitsYeong-Ruey Shieh, Cheng-Wen Wu. 120-126 [doi]
• A new method for testing mixed analog and digital circuitsJanusz Rzeszut, Bozena Kaminska, Yvon Savaria. 127-132 [doi]
• On the development of power supply voltage control testing technique for analogue circuitsA. K. B. A ain, A. H. Bratt, A. P. Dorey. 133-139 [doi]
• Tolerance DC bands of CMOS operational amplifierHassan Ihs, Christian Dufaza. 140 [doi]
• Theory and applications of cellular automata for synthesis of easily testable combinational logicS. Nandi, Parimal Pal Chaudhuri. 146-152 [doi]
• Unified scan design with scannable memory arraysSeiken Yano. 153-159 [doi]
• Test configurations to enhance the testability of sequential circuitsS. Lavabre, Yves Bertrand, Michel Renovell, Christian Landrault. 160-168 [doi]
• Test sequence compaction by reduced scan shift and retimingYoshinobu Higami, Seiji Kajihara, Kozo Kinoshita. 169-175 [doi]
• Testable design of non-scan sequential circuits using extra logicDebesh K. Das, Bhargab B. Bhattacharya. 176 [doi]
• Training diploma students on ATE-related moduleSudhir K. Jhajharia, Hua Swee Wang. 184 [doi]
• Panel: New Research Problems in the Emerging Test TechnologyVishwani D. Agrawal, Bernard Courtois, Fumiyasu Hirose, Sandip Kundu, Chung-Len Lee, Yinghua Min, P. Pal Chaudhuri. 189 [doi]
• A STAFAN-like functional testability measure for register-level circuitsC. P. Ravikumar, Gurjeet S. Saund, Nidhi Agrawal. 192-198 [doi]
• Testability forecasting for sequential circuitsShiyi Xu, Gercy P. Dias. 199-205 [doi]
• Testability analysis of co-designed systemsYves Le Traon, Chantal Robach. 206 [doi]
• Generator choices for delay testJacob Savir. 214-221 [doi]
• Static compaction for two-pattern test setsIrith Pomeranz, Sudhakar M. Reddy. 222-228 [doi]
• Identification of robust untestable path delay faultsWen Ching Wu, Chung-Len Lee, Jwu E. Chen. 229 [doi]
• An improved hierarchical test generation technique for combinational circuits with repetitive sub-circuitsDhruva R. Chakrabarti, Ajai Jain. 237-243 [doi]
• Deterministic test generation for non-classical faults on the gate levelUdo Mahlstedt, Jürgen Alt, Ingo Hollenbeck. 244-251 [doi]
• A parallel sequential test generation system DESCARTES based on real-valued logic simulationHiroshi Date, Michinobu Nakao, Kazumi Hatayama. 252-258 [doi]
• Universal test complexity of field-programmable gate arraysTomoo Inoue, Hideo Fujiwara, Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto. 259-265 [doi]
• Software transformations for sequential test generationArun Balakrishnan, Srimat T. Chakradhar. 266 [doi]
• Module level weighted random patternsJacob Savir. 274-278 [doi]
• A programmable multiple-sequence generator for BIST applicationsMeng-Lieh Sheu, Chung-Len Lee. 279-285 [doi]
• An effective BIST design for PLAJing-Yang Jou. 286-292 [doi]
• Fast computation of C-MISR signaturesManoj Franklin. 293-297 [doi]
• An effective BIST scheme for carry-save and carry-propagate array multipliersDimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian. 298-302 [doi]
• Error masking in compact testing based on the Hamming code and its modificationsSerge N. Demidenko, Alexander Ivanyukovich, Leonid Makhist, Vincenzo Piuri. 303 [doi]
• An efficient comparative concurrent Built-In Self-Test techniqueIoannis Voyiatzis, Dimitris Nikolos, Antonis M. Paschalis, Constantinos Halatsis, Th. Haniotakis. 309-315 [doi]
• Totally Self Checking reconfigurable duplication system with separate internal fault indicationNikolaos Gaitanis, Panagiotis Kostarakis, Antonis M. Paschalis. 316-321 [doi]
• Generalized modular design of testable m-out-of-n code checkerGosta Pada Biswas, Idranil Sen Gupta. 322-326 [doi]
• A graph coloring based approach for self-checking logic circuit designFadi Y. Busaba, Parag K. Lala. 327 [doi]
• Generation of tenacious tests for small gate delay faults in combinational circuitsHiroshi Takahashi, Takashi Watanabe, Yuzo Takamatsu. 332-338 [doi]
• Functional test generation for path delay faultsMandyam-Komar Srinivas, Vishwani D. Agrawal, Michael L. Bushnell. 339-345 [doi]
• Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuitsJason P. Hurst, Nick Kanopoulos. 346-352 [doi]
• Sequential logic path delay test generation by symbolic analysisSoumitra Bose, Vishwani D. Agrawal. 353 [doi]
• Low power design and its testabilityHiroaki Ueda, Kozo Kinoshita. 361-366 [doi]
• Power supply current detectability of SRAM defectsJian Liu, Rafic Z. Makki. 367 [doi]
• Fast functional testing of delay-insensitive circuitsSandeep Pagey. 375-381 [doi]
• DFT for fast testing of self-timed control circuitsSandeep Pagey, Ajay Khoche, Erik Brunvand. 382-386 [doi]
• Testing of a parallel ternary multiplier using I/sup 2/L logicMallika De, Bhabani P. Sinha. 387 [doi]