A simple technique for locating gate-level faults in combinational circuits

Teruhiko Yamada, Koji Yamazaki, Edward J. McCluskey. A simple technique for locating gate-level faults in combinational circuits. In 4th Asian Test Symposium (ATS 95), November 23-24, 1995. Bangalore, India. pages 65-70, IEEE Computer Society, 1995. [doi]

Abstract

Abstract is missing.