Chen-Shang Lin - researchr alias

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Viewing Publication 1 - 13 from 13

1997

Synthesis of Hazard-Free Asynchronous Circuits Based on Characteristic GraphKuan Jen Lin, Chi-Wen Kuo, Chen-Shang Lin. TC, 46(11):1246-1263, 1997.

1996

Parallel sequence fault simulation for synchronous sequential circuitsChen-Pin Kung, Chen-Shang Lin. et, 9(3):267-277, 1996. [doi]

1995

Test set compaction for combinational circuitsJau-Shien Chang, Chen-Shang Lin. tcad, 14(11):1370-1378, 1995. [doi]

Fast fault simulation for BIST applicationsChen-Pin Kung, Chun-Jieh Huang, Chen-Shang Lin. ats 1995: 93-99 [doi]

1994

A Test-Clock Reduction Method for Scan-Designed CircuitsJau-Shien Chang, Chen-Shang Lin. itc 1994: 331-339

HyHOPE: a fast fault simulator with efficient simulation of hypertrophic faultsChen-Pin Kung, Chen-Shang Lin. iccad 1994: 714-718 [doi]

Direct Synthesis of Hazard-Free Asynchronous Circuits from STGs Based on Lock Relation and BG-Decomposition ApproachKuan Jen Lin, Jih-Wen Kuo, Chen-Shang Lin. eurodac 1994: 178-183

1992

On the OBDD-Representation of General Boolean FunctionsHeh-Tyan Liaw, Chen-Shang Lin. TC, 41(6):661-664, 1992.

On the verification of state-coding in STGsKuan Jen Lin, Chen-Shang Lin. iccad 1992: 118-122 [doi]

1991

Automatic Synthesis of Asynchronous CircuitsKuan Jen Lin, Chen-Shang Lin. dac 1991: 296-301 [doi]

1990

Efficient Automatic Diagnosis of Digital CircuitsHeh-Tyan Liaw, Jia-Horng Tsaih, Chen-Shang Lin. iccad 1990: 464-467

1989

VVDS: A Verification/Diagnosis System for VHDLHeh-Tyan Liaw, K.-T. Tran, Chen-Shang Lin. dac 1989: 435-440 [doi]

1988

Automatic Functional Test Program Generation for MicroprocessorsChen-Shang Lin, Hong-Fa Ho. dac 1988: 605-608 [doi]

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