Abstract is missing.
- Design and Implementation of a High-Performance, Modular, Sorting EngineGeorge Alexiou, Dimitrios Stiliadis, Nick Kanopoulos. 2-8
- Design of a High Complexity Superscalar Microprocessor with the Portable IDPS ASIC LibraryAlain Greiner, L. Lucas, Franck Wajsbürt, Laurent Winckel. 9-13
- Taking Advantage of ASICs to Improve Dependability with Very Low OverheadsT. Michel, Régis Leveugle, Gabriele Saucier, R. Doucet, P. Chapier. 14-18
- Control flow optimization for fast system simulation and storage minimizationFrank H. M. Franssen, Lode Nachtergaele, H. Samsom, Francky Catthoor, Hugo De Man. 20-24
- Maximizing the Throughput of High Performance DSP Applications Using Behavioral TransformationsShan-Hsi Huang, Jan M. Rabaey. 25-30
- Instruction-Set Matching and Selection for DSP and ASIP Code GenerationClifford Liem, Trevor C. May, Pierre G. Paulin. 31-37
- Application of Simple Genetic Algorithms to Sequential Circuit Test GenerationElizabeth M. Rudnick, John G. Holm, Daniel G. Saab, Janak H. Patel. 40-45
- TORSIM: An Efficient Fault Simulator for Synchronous Sequential CircuitsSilvano Gai, Pier Luca Montessoro, Matteo Sonza Reorda. 46-50
- A Functional Approach to Delay Faults Test Generation for Sequential CircuitsFranco Fummi, Donatella Sciuto, Micaela Serra. 51-57
- Logic Synthesis and Verification of the CPU and Caches of a Mainframe SystemHuy Nam Nguyen, J. P. Tual, L. Ducousso, M. Thill, P. Vallet. 60-64
- ICM2 IC: a new ATM switching element for 2.48 Gb/s communicationsFermín Calvo, Pierre Plaza, Pedro Mateos. 65-69
- Advanced Analog Circuit Design on a Digital Sea-of-Gates ArrayR. van Dongen, V. Rikkink. 70-74
- Switched Current Sigma-Delta A/D Converter for a CMOS Subscriber Line Analog Front EndDorine Gevaert, Jozef Vanneuville, Jiri Nedved, Jan Sevenhans. 75-79
- Delay Reduction by Segment SubstitutionHitesh Ajuha, Premachandran R. Menon. 82-86
- Introduction of Permissible Bridges with Application to Logic Optimization after Technology MappingBernhard Rohfleisch, Franc Brglez. 87-93
- High-Level Synthesis of Digital Circuits by Finding FixpointsLakshmikanth Ghatraju, Mostafa H. Abd-El-Barr, Carl McCrosky. 94-98
- FPGA Partitioning for Critical PathsDaniel R. Brasen, Gabriele Saucier. 99-103
- A Low Cost BIST Methodology and Associated Novel Test Pattern GeneratorSen-Pin Lin, Sandeep K. Gupta, Melvin A. Breuer. 106-112
- Signature Analysis for Sequential Circuits with ResetAlbrecht P. Stroele. 113-118
- Fine-Grained Concurrency in Test Scheduling for Partial-Intrusion BISTIan G. Harris, Alex Orailoglu. 119-123
- A Fragmented Register Architecture and Test Advisor for BISTRichard Illman, D. J. Traynor. 124-129
- Bug Identification of a Real Chip Design by Symbolic Model CheckingBen Chen, Michihiro Yamazaki, Masahiro Fujita. 132-136
- A State Space Decomposition Algorithm for Approximate FSM TraversalHyunwoo Cho, Gary D. Hachtel, Enrico Macii, Massimo Poncino, Fabio Somenzi. 137-141
- An OBDD-Representation of StatechartsJohannes Helbig, Peter Kelb. 142-149
- A Functionality Fault Model: Feasibility and ApplicationsAndrej Zemva, Franc Brglez, Krzysztof Kozminski, Baldomir Zajc. 152-158
- Modeling of Broken Connections Faults in CMOS ICsMichele Favalli, Marcello Dalpasso, Piero Olivo, Bruno Riccò. 159-164
- Generating Test Patterns for Bridge Faults in CMOS ICsBrian Chess, Tracy Larrabee. 165-170
- A Hierarchical Approach to Fault CollapsingRalf Hahn, Rolf Krieger, Bernd Becker. 171-176
- Direct Synthesis of Hazard-Free Asynchronous Circuits from STGs Based on Lock Relation and BG-Decomposition ApproachKuan Jen Lin, Jih-Wen Kuo, Chen-Shang Lin. 178-183
- State Minimization of Pseudo Non-Deterministic FSM sYosinori Watanabe, Robert K. Brayton. 184-191
- Nondeterministic finite-state machines and sequential ::::don t cares::::Maurizio Damiani. 192-198
- Boolean Manipulation with Free BDD s. First Experimental ResultsJochen Bern, Jordan Gergov, Christoph Meinel, Anna Slobodová. 200-207
- An Extended OBDD Representation for Extended FSMsMichel Langevin, Eduard Cerny. 208-213
- Symbolic Algorithms to Calculate Steady-State Probabilities of a Finite State MachineGary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi. 214-218
- Self Testable Boards with Standard IEEE 1149.5 Module Test and Maintenance (MTM) Bus InterfaceOliver F. Haberl, Thomas Kropf. 220-225
- Random Testing of Interconnects in A Boundary Scan EnvironmentChauchin Su. 226-231
- Boundary Scan Testing Combined with Power Supply Current MonitoringMatti Kärkkäinen, Kari Tiensyrjä, Matti Weissenfelt. 232-235
- Implementation of a CORDIC Processor for CFFT Computation in Gallium Arsenide TechnologyRoberto Sarmiento, Kamran Eshraghian. 238-244
- PLFP256 A Pipelined Fourier ProcessorPierre Coulomb, François Pogodalla. 245-249
- A VLSI Implementation of Parallel Fast Fourier TransformA. Vacher, M. Benkhebbab, Alain Guyot, T. Rousseau, Ali Skaf. 250-255
- Design of a Digital Neural Chip: Application to Optical Character Recognition by Neural NetworkD. Jacquet, Gabriele Saucier. 256-260
- An Algorithm for Array Variable ClusteringLoganath Ramachandran, Daniel Gajski, Viraphol Chaiyakul. 262-266
- Transforming Linear Systems for Joint Latency and Throughout OptimizationMani B. Srivastava, Miodrag Potkonjak. 267-271
- Genesis: A Behavioral Synthesis System for Hierarchical TestabilitySandeep Bhatia, Niraj K. Jha. 272-276
- A Synthesis Method for Mixed Synchronous / Asynchronous BehaviorTsung-Yi Wu, Tzu-Chieh Tien, Allen C.-H. Wu, Youn-Long Lin. 277-281
- A New BIST Approach for Delay Fault TestingAnton Vuksic, Karl Fuchs. 284-288
- BIST Test Pattern Generators for Stuck-Open and Delay TestingChih-Ang Chen, Sandeep K. Gupta. 289-296
- Synthesis of Delay-Verifiable Two-Level CircuitsWuudiann Ke, Premachandran R. Menon. 297-301
- Synthesis of Sequential Machines with Reduced Testing CostSying-Jyan Wang. 302-306
- Incorporating the Controller Effects During Register Transfer Level SynthesisChampaka Ramachandran, Fadi J. Kurdahi. 308-313
- An Algorithm for Generation of Behavioral Shape FunctionsNancy D. Holmes, Daniel Gajski. 314-318
- Optimal Operation Scheduling Using Resource Lower Bound EstimationsMehmet Emin Dalkiliç, Vijay Pitchumani. 319-324
- Optimization of Address Generator HardwareDouglas M. Grant, Jef L. van Meerbergen, Paul E. R. Lippens. 325-329
- Predicting Circuit Performance Using Circuit-level Statistical Timing AnalysisRonn B. Brashear, Noel Menezes, Chanhee Oh, Lawrence T. Pillage, M. Ray Mercer. 332-337
- Towards Incorporating Device Parameter Variations in Timing AnalysisMukund Sivaraman, Andrzej J. Strojwas. 338-342
- A New Model to Uniformly Represent the Function and Timing of MOS Circuits and its Application to VHDL SimulationJürgen Frößl, Thomas Kropf. 343-348
- Taking Advantage of High Level Functional Information to Refine Timing Analysis and Timing ModelingC. Safinia, Régis Leveugle, Gabriele Saucier. 349-353
- Analysis of Bridging Defects in Sequential CMOS Circuits and their Current TestabilityRosa Rodríguez-Montañés, Joan Figueras. 356-360
- Transforming Sequential Logic in Digital CMOS ICs for Voltage and IDDQ TestingManoj Sachdev. 361-365
- Test of Bridging Faults in Scan-based Sequential CircuitsEugeni Isern, Joan Figueras. 366-370
- A Study of Undetectable Non-Feedback Shorts for the Purpose of Physical-DFTRichard McGowen, F. Joel Ferguson. 371-375
- A Generalized Signal Transition Graph Model for Specification of Complex InterfacesPeter Vanbekbergen, Chantal Ykman-Couvreur, Bill Lin, Hugo De Man. 378-384
- Interface Controller Synthesis from Requirement SpecificationsFranz Korf, Rainer Schlör. 385-394
- Synthesis of System-Level Bus InterfacesSanjiv Narayan, Daniel Gajski. 395-399
- A Genetic Algorithm for the Steiner Problem in a GraphHenrik Esbensen, Pinaki Mazumder. 402-406
- On Design Rule Correct Maze RoutingEd P. Huijbregts, Jos T. J. van Eijndhoven, Jochen A. G. Jess. 407-411
- An Efficient Router for 2-D Field Programmable Gate ArraysYu-Liang Wu, Malgorzata Marek-Sadowska. 412-416
- A Method for Reducing Power Consumption of CMOS Logic Based on Signal Transition ProbabilityJ. Akita, K. Asada. 420-424
- Cell Height Driven Transistor Sizing in a Cell Based Module DesignHow-Rern Lin, Ching-Lung Chou, Yu-Chin Hsu, TingTing Hwang. 425-429
- Non-Tree RoutingBernard A. McCoy, Gabriel Robins. 430-434
- Fault Modeling and Defect Level Projections in Digital ICsJosé T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Thomas W. Williams. 436-442
- Probability Analysis for CMOS Floating Gate FaultsHua Xue, Chennian Di, Jochen A. G. Jess. 443-448
- M-Testability: An Approach for Data-Path Testability EvaluationMohamed Jamoussi, Bozena Kaminska. 449-455
- A System-Design Methodology: Executable-Specification RefinementDaniel Gajski, Frank Vahid, Sanjiv Narayan. 458-463
- Interactive System-level Partitioning with PARTIFTarek Ben Ismail, Kevin O Brien, Ahmed Amine Jerraya. 464-468
- A Development Environment for the Cosynthesis of Embedded Software/Hardware SystemsMartyn Edwards, John Forrest. 469-473
- High-Level Design Validation Using Algorithmic DebuggingJiro Naganuma, Takeshi Ogura, Tamio Hoshino. 474-480
- Component Selection, Scheduling and Control Schemes for High Level SynthesisBruno Rouzeyre, D. Dupont, G. Sagnes. 482-489
- Optimal Scheduling and Software Pipelining of Repetitive Signal Flow Graphs with Delay Line OptimizationFrancis Depuydt, Werner Geurts, Gert Goossens, Hugo De Man. 490-494
- Scheduling with Environmental Constraints based on Automata RepresentationsJerry Chih-Yuan Yang, Giovanni De Micheli, Maurizio Damiani. 495-501
- Signal Type Optimisation in the Design of Time-Multiplexed DSP ArchitecturesKoen Schoofs, Gert Goossens, Hugo De Man. 502-506
- TRANS: A Fast and Memory-Efficient Path Delay Fault SimulatorMeng Chiy Lin, Jwu E. Chen, Chung-Len Lee. 508-512
- Efficient Path Identification for Delay Testing - Time and Space OptimizationHannes C. Wittmann, Manfred Henftling. 513-517
- Effectiveness of a Variable Sampling Time Strategy for Delay Fault DiagnosisD. Dumas, Patrick Girard, Christian Landrault, Serge Pravossoudovitch. 518-523
- Gate-Delay Fault Test with Conventional Scan-DesignArno Kunzmann, Frank Böhland. 524-528
- A Methodology for Analog Design Automation in Mixed-Signal ASICsStéphane Donnay, Koen Swings, Georges G. E. Gielen, Willy M. C. Sansen, Wim Kruiskamp, Domine Leenaerts. 530-534
- A Graphical Approach to Analogue Behavioural ModellingVincent Moser, Pascal Nussbaum, Hans Peter Amann, Luc Astier, Fausto Pellandini. 535-539
- An Overview of Analogue Optimisation Using AD-OPT Eamonn Byrne, Oliver McCarthy, David Lucas, Brian Donnellan. 540-545
- A Reduced-swing Data Transmission Scheme for Resistive Bus Lines in VSLIsMakoto Ikeda, Kunihiro Asada. 546-550
- Logic and Fault Simulation by Cellular AutomataYih-Lang Li, Cheng-Wen Wu. 552-556
- Variable Accuracy Device Modeling for Event-Driven Circuit SimulationKimon W. Michaels, Andrzej J. Strojwas. 557-561
- An Accurate Time-Domain Current Waveform Simulator for VLSI CircuitsJyh-Herng Wang, Jen-Teng Fan, Wu-Shiung Feng. 562-566
- An Efficient Yield Optimization Method Using A Two Step Linear Approximation of Circuit PerformanceZhihua Wang, Stephen W. Director. 567-571
- Efficient Implementations of Self-Checking Multiply and Divide ArraysMichael Nicolaidis, Hakim Bederr. 574-579
- Synthesis of Self-Testable ControllersSybille Hellebrand, Hans-Joachim Wunderlich. 580-585
- A Stepwise Refinement Data Path Synthesis Procedure for Easy TestabilityTaewhan Kim, Ki-Seok Chung, Chien-Liang Liu. 586-590
- Automatic Synthesis of BISTed Data Paths From High Level SpecificationMarie-Lise Flottes, D. Hammad, Bruno Rouzeyre. 591-598
- HANDICAP - A System for Design ConsultingM. Straube, Wolfgang Wilkes, Gunter Schlageter. 600-604
- Flow Management Requirements of a Test Harness for Testing the Reliability of an Electronic CAD SystemGunnar Bartels, Peter Kist, Kees Schot, Mattie Sim. 605-609
- Distributed Computing, Automatic Design, and Error Recovery in the ULYSSES II FrameworkSandip Parikh, David Sarnoff, Michael L. Bushnell, James Sienicki, Ramakrishnan Ganesh. 610-617
- Minimizing ROBDD Size of Incompletely Specified Multiple Output FunctionsShih-Chieh Chang, David Ihsin Cheng, Malgorzata Marek-Sadowska. 620-624
- Timing Analysis of Combinational Circuits using ADD sR. Iris Bahar, Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Fabio Somenzi. 625-629
- Efficient Calculation of Boolean Relations for Multi-Level Logic OptimizationBernd Wurth, Norbert Wehn. 630-634
- System-Level Modeling and Verification: a Comprehensive Design MethodologyPaolo Camurati, Fulvio Corno, Paolo Prinetto, Catherine Bayol, Bernard Soulas. 636-640
- Clean formal semantics for VHDLPeter T. Breuer, Luis Sánchez Fernández, Carlos Delgado Kloos. 641-647
- Control Path Oriented Verification of Sequential Generic Circuits with Control and Data PathKlaus Schneider, Thomas Kropf, Ramayya Kumar. 648-652
- The Russian EDA Standards ActivitiesN. M. Vitsyn. 654
- Underground Capacitors Very Efficient Decoupling for High Performance UHF Signal Processing ICsThomas Johansson, L. R. Virtanen, J. M. Gobbi. 655
- Design of a Real Time Geometric ClassifierMichel Robert, P. Gorria, Johel Mitéran, S. Turgis. 656
- From Behavioral Description to Systolic Array Based ArchitecturesAlessandro Balboni, Claudio Costi, Franco Fummi, Donatella Sciuto. 657
- Estimation of Simultaneous Switching Power and Ground Noise of Static CMOS Combinational CircuitsAbdessatar Abderrahman, Bozena Kaminska, Yvon Savaria. 658
- AREAL: Automated Reasoning Expert for Analogue LayoutH. H. Ahmad, R. J. Mack. 659
- An Optimizable Model for Process Independent Symbolic DesignJean-Claude Dufourd, Jean-François Naviner. 660
- Distributed Fault Simulation for Sequential Circuits by Pattern PartitioningWen Ching Wu, Chung-Len Lee, Jwu E. Chen, Won Yih Lin. 661
- A Suggestion for Accelerating the Analog Fault SimulationWolfgang Vermeiren, Bernd Straube, Günter Elst. 662
- Software Implementation and Statistical Optimization of Some Electronic Component s LifetimeK. C. Koudakou. 663
- Physical Modeling of Linearity Errors for the Diagnosis of High Resolution R-2R D/A ConvertersAndrea Boni, G. Chiorboli, G. Franco, S. Mazzoleni, M. Ostacoli. 664
- A Model-based Approach to Analog Fault Diagnosis using Techniques from OptimisationSalman Ahmed, Peter Y. K. Cheung, Phil Collins. 665
- Functional Tests for Ring-Address SRAM-type FIFOsA. J. van de Goor, Yervant Zorian, Ivo Schanstra. 666
- Testability of Circuits Derived from Functional Decision DiagramsBernd Becker, Rolf Drechsler. 667
- A Redefinable Symbolic Simulation Technique to Testability Design Rules CheckingM. Hirech, O. Florent, Alain Greiner, E. Rejouan. 668
- Multilevel Logic Synthesis of Very High Complexity CircuitsLuc Burgun, N. Dictus, Alain Greiner, E. Pradho, C. Sarwary. 669
- Signal Transition Graph Transformations for InitializabilitySavita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar, Dhiraj K. Pradhan. 670
- Synthesis of Application-Specific Multiprocessor SystemsMuhammad K. Dhodhi, Imtiaz Ahmad, C. Y. Roger Chen. 671
- Generating Synchronous Timed Descriptions of Digital Receivers from Dynamic Data Flow System Level ConfigurationsPeter Zepter, Thorsten Grötker. 672