Rabindra K. Roy - researchr alias

researchr

You are not signed in
Sign in
Sign up

Viewing Publication 1 - 41 from 41

2000

EDA challenges facing future microprocessor designT. Karn, Shishpal Rawat, Desmond Kirkpatrick, Rabindra K. Roy, Greg Spirakis, Naveed A. Sherwani, Craig Peterson. tcad, 19(12):1498-1506, 2000. [doi]

1999

Characterizing Individual Gate Power Sensitivity in Low Power DesignUnni Narayanan, Georgios I. Stamoulis, Rabindra K. Roy. vlsid 1999: 625

Partial Reset Methodology and Experiments for Improving Random-Pattern Testability and BIST of Sequential CircuitsHuy Nguyen, Rabindra K. Roy, Abhijit Chatterjee. et, 14(3):259-272, 1999. [doi]

1998

Considering Testability during High-level Design (Embedded Tutorial)Sujit Dey, Anand Raghunathan, Rabindra K. Roy. aspdac 1998: 205-210

Activity Measures for Fast Relative Power Estimation in Numerical Transformation for Low Power DSP SynthesisHuy T. Nguyen, Abhijit Chatterjee, Rabindra K. Roy. vlsisp, 18(1):25-38, 1998. [doi]

Partial Reset Methodologies for Improving Random-Pattern Testability and BIST of Sequential CircuitsHuy Nguyen, Rabindra K. Roy, Abhijit Chatterjee. vlsid 1998: 199-204

Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path CircuitsSrivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey. et, 13(2):201-212, 1998. [doi]

Controller Resynthesis for Testability Enhancement of RTL Controller/Data path CircuitsSrivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey. vlsid 1998: 193-198 [doi]

1997

Concurrent Error Detection in Nonlinear Digital Circuits Using Time-Freeze LinearizationAbhijit Chatterjee, Rabindra K. Roy. TC, 46(11):1208-1218, 1997.

Impact of Partial Reset on Fault Independent Testing and BISTHuy Nguyen, Abhijit Chatterjee, Rabindra K. Roy. vlsid 1997: 537-539 [doi]

1996

Synchronous Test Generation Model for Asynchronous CircuitsSavita Banerjee, Srimat T. Chakradhar, Rabindra K. Roy. vlsid 1996: 178-185 [doi]

Initialization issues in asynchronous circuit synthesisSavita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar. et, 9(3):237-250, 1996. [doi]

Synthesis of initializable asynchronous circuitsSrimat T. Chakradhar, Savita Banerjee, Rabindra K. Roy, Dhiraj K. Pradhan. tvlsi, 4(2):254-263, 1996. [doi]

1995

1994

Initialization Isuues in the Synthesis of Asynchronous CircuitsSavita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar, Dhiraj K. Pradhan. iccd 1994: 447-452

Signal Transition Graph Transformations for InitializabilitySavita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar, Dhiraj K. Pradhan. eurodac 1994: 670

Synthesis of Initializable Asynchronous CircuitsSrimat T. Chakradhar, Savita Banerjee, Rabindra K. Roy, Dhiraj K. Pradhan. vlsid 1994: 383-388

Design for diagnosability of linear digital filters using time-space expansionAbhijit Chatterjee, Rabindra K. Roy. vts 1994: 48-53 [doi]

Synthesis of Low Power Linear DSP Circuits Using Activity MetricsAbhijit Chatterjee, Rabindra K. Roy. vlsid 1994: 265-270

Guest Editor s Introduction: Practical Asynchronous DesignTam Anh Chu, Rabindra K. Roy. dt, 11(2):6-7, 1994. [doi]

Behavioral synthesis of low-cost partial scan designs for DSP applicationsSujit Dey, Miodrag Potkonjak, Rabindra K. Roy. icassp 1994: 441-444 [doi]

Synthesizing designs with low-cardinality minimum feedback vertex set for partial scan applicationSujit Dey, Miodrag Potkonjak, Rabindra K. Roy. vts 1994: 2-7 [doi]

1993

1992

1991

The Best Flip-Flops to ScanMiron Abramovici, James J. Kulikowski, Rabindra K. Roy. itc 1991: 166-173

Efficient testing strategies for bit- and digit-serial arrays used in digital signal processorsAbhijit Chatterjee, Rabindra K. Roy, Jacob A. Abraham, Janak H. Patel. dsp, 1(4):231-244, 1991. [doi]

1990

Timing verification and synthesis of circuits for delay fault testabilityRabindra K. Roy. PhD thesis, University of Illinois Urbana-Champaign, USA, 1990. [doi]

1989

Dynamic redundancy identification in automatic test generationMiron Abramovici, David T. Miller, Rabindra K. Roy. iccad 1989: 466-469 [doi]

1988

Fault Simulation in a Distributed EnvironmentPatrick A. Duba, Rabindra K. Roy, Jacob A. Abraham, William A. Rogers. dac 1988: 686-691 [doi]

Compaction of ATPG-generated test sequences for sequential circuitsRabindra K. Roy, Thomas M. Niermann, Janak H. Patel, Jacob A. Abraham, Resve A. Saleh. iccad 1988: 382-385 [doi]

All Publications

Filter by Year
OR AND NOT 1

Filter by Type
OR AND NOT 1

Filter by Tag
OR AND NOT 1

Filter by Venue
OR AND NOT 1

Filter by Author

[+]
OR AND NOT 1

Filter by Top Terms

[+]
OR AND NOT 1

Researchr

Publications by 'Rabindra K. Roy'

Viewing Publication 1 - 41 from 41

2000

1999

1998

1997

1996

1995

1994

1993

1992

1991

1990

1989

1988

All Publications

Filter by YearOR AND NOT 1

Filter by TypeOR AND NOT 1

Filter by TagOR AND NOT 1

Filter by VenueOR AND NOT 1

Filter by Author [+]OR AND NOT 1

Filter by Top Terms [+]OR AND NOT 1

Researchr

Publications by 'Rabindra K. Roy'

Viewing Publication 1 - 41 from 41

2000

1999

1998

1997

1996

1995

1994

1993

1992

1991

1990

1989

1988

Filter by Year
OR AND NOT 1

Filter by Type
OR AND NOT 1

Filter by Tag
OR AND NOT 1

Filter by Venue
OR AND NOT 1

Filter by Author

[+]
OR AND NOT 1

Filter by Top Terms

[+]
OR AND NOT 1