Table of Contents

• Intel and the Myths of TestKenneth M. Thompson. 10
• Design and Testing of the On-Ramps to the Information SuperhighwayPhilippe Chauveau. 11
• Exact Aliasing Computation for RAM BISTO. Kebichi, Michael Nicolaidis, Vyacheslav N. Yarmolik. 13-22
• Synthesized Transparent BIST for Detecting Scrambled Pattern-Sensitive Faults in RAMsBruce F. Cockburn, Y.-F. Nicole Sat. 23-32
• Deterministic Self-Test of a High-Speed Embedded Memory and Logic Processor SubsystemLuigi Ternullo Jr., R. Dean Adams, John Connor, Garret S. Koch. 33-44
• Upset-Tolerant CMOS SRAM Using Current Monitoring: Prototype and Test ExperimentsTh. Calin, F. L. Vargas, Michael Nicolaidis. 45-53
• The Use of Linear Models for the Efficient and Accurate Testing of A/D ConvertersPeter D. Capofreddi, Bruce A. Wooley. 54-60
• Industrial Relevance of Analog IFA: A Fact or a FictionManoj Sachdev, Bert Atzema. 61-70
• A Comparative Analysis of Input Stimuli for Testing Mixed-Signal LSIs Based on Curent TestingYukiya Miura. 71-77
• Arbitrary-Precision Signal Generation for Bandlimited Mixed-Signal TestingXavier Haurie, Gordon W. Roberts. 78-86
• Visualizing QualitySolomon Max. 87-96
• A General Purpose ATE Based I::DDQ:: Measurement CircuitGerald H. Johnson, Jan B. Wilstrup. 97-105
• SiPROBE - A New Technology for Wafer ProbingKarl F. Zimmermann. 106-112
• Parallel Delay Fault Coverage and Test Quality EvaluationIra Pramanick, Ankan K. Pramanick. 113-122
• Non-Robust versus RobustAlicja Pierzynska, Slawomir Pilarski. 123-131
• Test Vector Generation for Parametric Path Delay FaultsMukund Sivaraman, Andrzej J. Strojwas. 132-138
• Classification and Test Generation for Path-Delay Faults Using Single Stuck-Fault TestsMarwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal. 139-148
• Test Generation and Design for Test for a Large Multiprocessing DSPGraham Hetherington, Greg Sutton, Kenneth M. Butler, Theo J. Powell. 149-156
• Testability, Debuggability, and Manufacturability Features of the UltraSPARC:::TM:::-I MicroprocessorMarc E. Levitt, Srinivas Nori, Sridhar Narayanan, G. P. Grewal, Lynn Youngs, Anjali Jones, Greg Billus, Siva Paramanandam. 157-166
• Overview of PowerPC:::TM::: 620 Multiprocessor Verification StrategyJen-Tien Yen, Marie Sullivan, Carlos Montemayor, Pete Wilson, Richard Evers. 167-174
• Structured Design-for-Debug - The SuperSPARC:::TM::: II Methodology and ImplementationHong Hao, Rick Avra. 175-183
• A Novel Low-Cost Approach to MCM Interconnect TestBruce C. Kim, Abhijit Chatterjee, Madhavan Swaminathan, David E. Schimmel. 184-192
• Integrated Test Solutions and Test Economics for MCMsKevin T. Kornegay, Kaushik Roy. 193-201
• A Comparison of Test Requirements, Methods, and Results for Seven MCM ProductsAndrew Flint. 202-207
• Distributed Probabilistic Diagnosis of MCMs on Large AreaKoppolu Sasidhar, Abhijit Chatterjee, Vinod K. Agarwal, Joseph L. A. Hughes. 208-216
• Matching Models to Real Life for Defect ReductionJames A. Tuttle, Thomas W. Collins, Mary Stone Tuttle. 217-223
• Test SPC: A Process to Improve Test System IntegrityWillie Benitez, Deo Marrero, Douglas J. Mirizzi, Dale Ohmart. 224-232
• User Application of Statistical Process Monitor Techniques to ASIC Critical ParametersAlex M. Ijaz, Eugene R. Hnatek. 233-241
• A Test Data Collection System for Uniform Data AnalysisSusan D. Shaye. 242-251
• Coping with Re-usability Using Sequential ATPG: A Practical Case StudyJos van Sas, Erik Huyskens, Hans Naert, Fred Schell, A. J. van de Goor. 252-261
• DFT & ATPG: Together AgainBen Mathew, Daniel G. Saab. 262-271
• Low-Complexity Fault Simulation under the Multiplie Observation Time Testing ApproachIrith Pomeranz, Sudhakar M. Reddy. 272-281
• A Fault Model and a Test Method for Analog Fuzzy Logic CircuitsStefan Weiner. 282-291
• A Designer s View of Chip TestThomas L. Anderson. 292
• Advantages of High-Level Test Synthesis over Design for TestRabindra K. Roy. 293
• Is High-Level Test Synthesis Just Design for Test?Christian Landrault, Marie-Lise Flottes, Bruno Rouzeyre. 294
• The Many Faces of Test SynthesisPeter C. Maxwell. 295
• The Case for Contract ManufacturingRandall Hassig. 296
• Contract Manufacturing: How Much Can They Do?Tom Langford. 297
• Re-examining the Needs of the Mixed-Signal TestGordon W. Roberts. 298
• Stuck-at Faults, PPMs Rejects or? What doe the SIA Roadmaps Say?Keith Baker. 299
• The Final Barriers to Widespread Use of I::DDQ:: TestingJohn M. Acken. 300
• Test Quality: Required Stuck-at Fault Coverage with the Use of I::DDQ:: TestingRon Wantuck. 301
• High-Performance Circuit Testing with Slow-Speed TestersVishwani D. Agrawal, Tapan J. Chakraborty. 302-310
• Avoiding Unknown States When Scanning Mutually Exclusive LatchesStephen Pateras, Martin S. Schmookler. 311-318
• A Hierarchical, Desgin-for-Testability (DFT) Methodology for the Rapid Prototyping of Application-Specific Signal Processors (RASSP)Richard M. Sedmak, John Evans. 319-327
• Supplying Known-Good Die for MCM Applications Using Low-Cost Embedded TestingA. Frisch, Mitch Aigner, T. Almy, Hans J. Greub, M. Hazra, S. Mohr, Nicholas J. Naclerio, W. Russell, M. Stebniskey. 328-335
• IC Performance Prediction SystemV. Ramakrishnan, D. M. H. Walker. 336-344
• An Approach for Designing Total-Dose Tolerant MCMs Based on Current MonitoringFabian Vargas, Michael Nicolaidis, Yervant Zorian. 345-354
• Improving DSP-Based Measurements with Spectral InterpolationMark Burns. 355-363
• THD and SNR Tests Using the Simplified Volterra Series with Adaptive AlgorithmsLuke S. L. Hsieh, Andrew Grochowski. 364-369
• Increasing Test Throughput Through the Implementation of Parallel Test on a 16-Bit Multimedia Audio CODECHarold Bogard, Celeste Repasky. 370-376
• Improvement of the Defect Level of Micro-computer LSI TestingJunichi Hirase. 377-383
• In-System Testing of Cache MemoriesJanusz Sosnowski. 384-393
• Towards 100 Testable FIR Digital FiltersLaurence Goodby, Alex Orailoglu. 394-402
• An Efficient and Economic Partitioning Approach for TestabilityXinli Gu, Krzysztof Kuchcinski, Zebo Peng. 403-412
• A New Method for Partial Scan Design Based on Propagation and Justification Requirements of FaultsInsung Park, Dong Sam Ha, Gyoochan Sim. 413-422
• On Combining Design for Testability TechniquesPrashant S. Parikh, Miron Abramovici. 423-429
• MCM Quality and Cost Analysis Using Economics ModelsChryssa Dislis, A. F. Al-Ani, Ian P. Jalowiecki. 430-437
• Study on the Costs of On-site VLSI TestingJunichi Hirase. 438-443
• The P1149.4 Mixed Signal Test Bus: Costs and BenefitsStephen K. Sunter. 444-450
• A Gate-Array-Based 666MHz VLSI Test SystemShuji Kikuchi, Yoshihiko Hayashi, Takashi Suga, Jun Saitou, Masahiko Kaneko, Takashi Matsumoto, Ryozou Yoshino. 451-458
• A Low-Cost High-Performance CMOS Timing Vernier for ATEJim Chapman, Jeff Currin, Steve Payne. 459-468
• Evaluating Waveform-Generation Capabilities of VLSI Test SystemsMichael G. Davis. 469-478
• I::DDQ:: Testing of CMOS Opens: An Experimental StudyAdit D. Singh, Haroon Rasheed, Walter W. Weber. 479-489
• Production I::DDQ:: Testing with Passive Current CompensationGregory A. Maston. 490-497
• Finding Defects with Fault ModelsRobert C. Aitken. 498-505
• Timing-Driven Test Point Insertion for Full-Scan and Partial-Scan BISTKwang-Ting Cheng, Chih-Jen Lin. 506-514
• Test Point Insertion for an Area Efficient BISTClaus Schotten, Heinrich Meyr. 515-523
• Performance Driven BIST Technique for Random LogicCharles Njinda, Neeraj Kaul. 524-533
• I::DDQ:: and Voltage Testable CMOS Flip-flop ConfigurationsManoj Sachdev. 534-543
• A Detailed Analysis of GOS Defects in MOS Transistors: Testing Implications at Circuit LevelJaume Segura, Carol de Benito, A. Rubio, Charles F. Hawkins. 544-551
• Inductive Contamination Analysis (ICA) with SRAM ApplicationJitendra Khare, Wojciech Maly. 552-560
• Algorithmic Extraction of BSDL from 1149.1-compliant Sample ICsDouglas W. Raymond, D. Eugene Wedge, Philip J. Stringer, Harold W. Ng, Suzanne T. Jennings, Craig T. Pynn, Winsor Soule Jr.. 561-568
• Integration of IEEE Std. 1149.1 and Mixed-Signal Test ArchitecturesDavid J. Cheek, Ramaswami Dandapani. 569-576
• Improving Board and System Test: A Proposal to Integrate Boundary Scan and I::DDQ::Douglas Reed, Jason Doege, Antonio Rubio. 577-585
• High-Level Test Generation Using Symbolic SchedulingMark C. Hansen, John P. Hayes. 586-595
• Hierarchical Functional-Fault Simulation for High-Level SynthesisMark Kassab, Janusz Rajski, Jerzy Tyszer. 596-605
• Functional Tests for Scan Chain LatchesSamy Makar, Edward J. McCluskey. 606-615
• On Efficiently and Reliably Achieving Low Defective Part LevelsLi-C. Wang, M. Ray Mercer, Thomas W. Williams. 616-625
• Yiel Learning via Functional Test DataYoung-Jun Kwon, D. M. H. Walker. 626-635
• Failure Analysis for Full-Scan CircuitsKaushik De, Arun Gunda. 636-645
• A Discussion of Methods for Measuring Low-Amplitude JitterMichael K. Williams. 646-652
• An Experimental Chip to Evaluate Test Techniques: Chip and Experiment DesignPiero Franco, William D. Farwell, Robert L. Stokes, Edward J. McCluskey. 653-662
• An Experimental Chip to Evaluate Test Techniques: Experiment ResultsSiyad C. Ma, Piero Franco, Edward J. McCluskey. 663-672
• Using the Right Tools and Techniques leads to Successful Testing of MCMsAndrew Flint. 673
• Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BISTNur A. Touba, Edward J. McCluskey. 674-682
• Synthesis and Retiming for the Pseudo-Exhaustive BIST of Synchronous Sequential CircuitsSamir Lejmi, Bozena Kaminska, Bechir Ayari. 683-692
• Test Synthesis in the Behavioral DomainChristos A. Papachristou, Joan Carletta. 693-702
• Software Test Data Generation Using the Chaining ApproachRoger Ferguson, Bogdan Korel. 703-709
• From Hardware to Software TestabilityYves Le Traon, Chantal Robach. 710-719
• On the Use of Neural Networks to Guide Software Testing ActivitiesCharles Anderson, Anneliese Amschler Andrews, Richard T. Mraz. 720-729
• Dynamic Program Complexity and Software TestingJohn C. Munson, Gregory A. Hall. 730-737
• Test Synthesis: From Wishful Thinking to RealityKamalesh N. Ruparel. 738
• Plug & Play I::DDQ:: Monitoring with QTAGKeith Baker, T. F. Waayers, F. G. M. Bouwman, M. J. W. Verstraelen. 739-749
• IntegraTEST: The New Wave in Mixed-Signal TestBirger Schneider, Soeren Soegaard. 750-760
• Dynamic Test Emulation for EDA-Based Mixed-Signal Test Development AutomationJean Qincui Xia, Tom Austin, Nash Khouzam. 761-770
• Report on a Pilot Project Successfully Implementing a Design-to-Test MethodologyScot Bullock. 771-780
• A Routing Testing of a VLSI Massively Parallel Machine Based on IEEE 1149.1Chouki Aktouf, Chantal Robach, A. Marinescu. 781-788
• A Secure Data Transmission Scheme for 1149.1 Backplane Test BusWuudiann Ke, Duy Le, Najmi T. Jarwala. 789-796
• Leave the Wires to Last - Funcitonal Evaluation of the IEEE Std 1149.5 Module Test and Maintenance BusRodham E. Tulloss. 797-806
• Cost-Effective System-Level Test StrategiesDes Farren, Anthony P. Ambler. 807-813
• A Methodology to Design Efficient BIST Test Pattern GeneratorsChih-Ang Chen, Sandeep K. Gupta. 814-823
• An Effective BIST Scheme for Booth MultipliersDimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian. 824-833
• Optimal Space Compaction of Test ResponsesKrishnendu Chakrabarty, Brian T. Murray, John P. Hayes. 834-843
• Implementing 1149.1 in the PowerPC:::TM::: RISC Microprocessor FamilyCarol Pyron, W. C. Bruce. 844-850
• Improved Boundary Scan DesignLee Whetsel. 851-860
• Compiled Code, Dynamic Worst Case Timing Simulation Tracking Multiple CausalityKamal K. Varma. 861-869
• Challenging the High Performance - High Cost Paradigm in TestUlrich Schoettmer, Toshiyuki Minami. 870-879
• A Single Board Test System: Changing the Test ParadigmGarry C. Gillette. 880-885
• A Tester for Design:::TM::: (TFD)Gary J. Lesmeister. 886-891
• Transient Power Supply Current Testing of Digital CMOS CircuitsRafic Z. Makki, Shyang-Tai Su, Troy Nagle. 892-901
• Intel 386:::TM::: EX Embedded Processor I::DDQ:: TestingHitesh Ahuja, Dean Arriens, Ben Schneller, Vandana Verma, Wendy Whitman. 902-909
• On the Effect of I::SSQ:: Testing in Reducing Early Failure RateKenneth M. Wallquist. 910-915
• Solving Known Good Die (and Substrate) Test IssuesAlan W. Righter. 916
• Electrical Troubleshooting, Diagnostics, and Repair of Multichip ModulesDavid C. Keezer. 917
• Required - A Portable Test StandardLawrence D. Carpenter. 918
• STIL from the Users PerspectiveGregory A. Maston. 919
• It s DFT, Boundary Scan and Life Cycle BenefitsGary O Donnell. 920
• Cutting the Cost of Test; the Value-added WayWilliam R. Simpson. 921
• Optimizing Product Profitability - The Test WayPrab Varma. 922
• Deep Submicron: Is Test Up to the Challenge?Kenneth M. Butler. 923
• What s So Different about Deep-Submicron Test?Craig Hunter. 924
• The ITC Lecture Series: An ExperimentKenneth P. Parker, David Greene. 925
• Finding I/O Faults on In-Circuit ICs Using Parasitic Transistor TestsJack Ferguson. 926
• Two New Techniques for Identifying Opens on Printed Circuit Boards: Analog Junction Test & Radio Frequency Induction TestJoe Wrinn. 927
• Capacitive Leadframe TestingTed T. Turner. 928
• Telecom Test: New Challenges, Old RootsJames Jamieson. 929
• A Bulti-in Self-Test Strategy for Wireless Communication SystemsBenoît R. Veillette, Gordon W. Roberts. 930-939
• End-to-End Test Strategy for Wireless SystemsMadhuri Jarwala, Duy Le, Michael S. Heutmaker. 940-946
• Testing a Switching Memory in a Telcommunication SystemStefano Barbagallo, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda. 947-956
• Automated 1.5 GHz Sonet CharacterizationRob Tepper, Jim Tarpo. 957-965
• Development of an ATE Test Station for Mixed CATV/TELCO ProductsMichael T. Freeman. 966-972
• Optimizing Test Strategies for SONET/SDH/ATM Network Element ManufacturingMark Hoogerbrugge. 973-978
• End-to-End Performance Measurement for Interactive Multimedia TelevisionMartin A. Schulman. 979-985
• Linking Diagnostic Software to Hardware Self Test in Telecom SystemsHarry Hulvershorn, Paul Soong, Saman Adham. 986-993
• A New Hardware Fault Insertion Scheme for System Diagnostics VerificationBenoit Nadeau-Dostie, Harry Hulvershorn, Saman Adham. 994-1002