Table of Contents

• On the History and Future Detecion of VLSI Design and CAD - Japanese PerspectiveOsamu Karatsu. 3-4
• A Heuristic for Decomposition in Multi-Level Logic OptimizationVinaya Kumar Singh, A. A. Diwan. 5-8
• Combining State Assignment with PLA FoldingChunduri Rama Mohan, Partha Pratim Chakrabarti, Sujoy Ghose. 9-14
• State Assignment for Optimal Design of Monitored Self-Checking Sequential CircuitsRubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar. 15-20
• Synthesis of Hazard-free Asynchronous Circuits from Generalized Signal-Transition GraphsAlexandre Yakovlev. 21-24
• SIGMA: A VLSI Chip for Galois Field GF(2:::m:::) Based Multiplication and DivisionMario Kovac, N. Ranganathan, M. Varanasi. 25-30
• A Partition Approach to Find the Length of the Longest Common SubsequenceChowdhury S. Rahman, Mi Lu. 31-36
• Design of an On-Line Euclidean ProcessorR. Bouraoui, Alain Guyot, G. Walker. 37-40
• Hardware Algorithms for Polygon MatchingRaghu Sastry, N. Ranganathan, Horst Bunke. 41-44
• Heuristics for the Placement of Flip-Flops in Partial Scan Designs and the Placement of Signal Boosters in Lossy CircuitsDoowon Paik, Sudhakar M. Reddy, Sartaj Sahni. 45-50
• A DFT Technique to Improve ATPG Efficiency for Sequential CircuitsYves Bertrand, Frédéric Bancel, Michel Renovell. 51-54
• Statistical Analysis of ControllabilityAmitava Majumdar, Sarma Sastry. 55-60
• CACOP - A Random Pattern Testability AnalyzerWen-Ben Jone, Sunil R. Das. 61-64
• On the Generation of Weights for Weighted Pseudo Random TestingIrith Pomeranz, Sudhakar M. Reddy. 69-72
• FLOR: A Hierarchical Floorplanner Under Vinyas VCX System - System OverviewSuhail Ahmed, T. V. Nagesh, Ramoji Rao, B. Naveen, P. K. Fangaria, K. S. Raghunathan. 73-79
• NP-Completeness of Multi-Layer No-Dogleg Channel Routing and an Efficient HeuristicRajat K. Pal, Sudebkumar Prasant Pal, Ajit Pal, Alak K. Dutta. 80-83
• Euclidean Shortest Path Problem with Rectilinear ObstaclesJoon Shik Lim, S. Sitharama Iyengar, Si-Qing Zheng. 90-93
• On Optimum Cell Models for Over-the-Cell RoutingSiddharth Bhingarde, Anand Panyam, Naveed A. Sherwani. 94-99
• Efficient Technique to Reduce Gate Evaluations and Speed Up Fault SimulationP. R. Suresh Kumar, Mandyam-Komar Srinivas, James Jacob. 104
• A PLA-Based FSM Design TechniqueS. Raman, M. M. Hasan. 105-106
• Synthesis of Self-Checking Sequential Machines Using Cellular AutomataDipanwita Roy Chowdhury, Supratik Chakraborty, Parimal Pal Chaudhuri. 107
• Via Minimization in Channel Routing by Layout ModificationSandip Das, Bhargab B. Bhattacharya. 109-110
• High Level Design Experiences with IDEASC. S. Ajay, M. Balakrishnan, D. Harikrishna, M. Karunakaran, Anshul Kumar, Shashi Kumar, V. Mudgil, A. R. Naseer. 110
• BEST: Bond Editor and Test Vector TranslatorP. Marimuthu, K. S. Raghunathan. 111
• A Scheme for Synthesizing Testable VLSI Designs with Minimum Area OverheadBiswadip Mitra, Parimal Pal Chaudhuri. 112
• A Provably Good Algorithm for ::::k::::-Layer Topological Planar Routing ProblemsJason Cong, Moazzem Hossain, Naveed A. Sherwani. 113
• Preparing Engineers to Meet the Challenges of the 21st Century Through VLSI EducationKanti Prasad, Aditya Goel. 114-117
• Use of Storage Elements as Primitives for Modelling Faults in Synchronous Sequential CircuitsW. K. Al-Assadi, Yashwant K. Malaiya, Anura P. Jayasumana. 118-123
• A Hierarchical Test Generation Using High Level PrimitivesD. Crestani, A. Aguila, L. Eudeline, M.-H. Gentil, C. Durante. 124-127
• FAST-SC: Fast Fault Simulation in Synchronous Sequential CircuitsBernd Becker, Rolf Krieger. 128-131
• A Simulation-Based Test Generation Scheme Using Genetic AlgorithmsM. Srinivas, Lalit M. Patnaik. 132-135
• Coverage of Bridging Faults by Random Testing in I::DDQ:: Test EnvironmentRochit Rajsuman, D. A. Penry. 136-139
• Automatic Test Plan Generation for Analog Integrated Circuits - A Practical ApproachRavindranath Naiknaware, G. N. Nandakumar, Rajeev Arora, John Larkin. 140-143
• Algorithm-Based Concurrent Error Detection for FFT NetworksChoong Gun Oh, Hee Yong Youn, Vijay K. Raj. 144-147
• Rate-Optimal DSP Synthesis by Pipeline and Minimum UndoldingLih-Gwo Jeng, Liang-Gee Chen. 148-153
• Greedy Hardware Optimization for Linear Digital Systems Using Number SplittingAbhijit Chatterjee, Rabindra K. Roy, Manuel A. d Abreu. 154-159
• A Simplified High Speed Parallel Input ConvolverLuigi Dadda. 160-165
• A Reconfigurable Arithmetic ProcessorArjun Rajagopal, Belli Kuttanna, Balaji Janakiraman, Rajarshi Mukherjee, Joy Shetler. 172-175
• A Methodology for Generating Application Specific Tree MultipliersS. Ramanathan, Nibedita Mohanty, V. Visvanathan. 176-179
• GB: A New Grid-Based Binding Approach for High-Level SynthesisHyuk-Jae Jang, Barry M. Pangrle. 180-185
• Self-Organization and its Application to BindingAhmed Hemani. 186-191
• An Integrated and Accelerated ILP Solution for Scheduling, Module Allocation, and Binding in Datapath SynthesisThomas Charles Wilson, Nilanjan Mukherjee, M. K. Garg, Dilip K. Banerji. 192-197
• Harmonic Scheduling: A Technique for Scheduling Beyond Loop-Carried DependenciesHaigeng Wang, Nikil D. Dutt, Alexandru Nicolau. 198-201
• ::::MS:::::::3:::: Micro-Rollback and Self-Recovery System SynthesisByung Wook Jeon, Chidchanok Lursinsap. 202-207
• Genetic Beam Search for Gate Matrix LayoutKhushro Shahookar, W. Khamisani, Pinaki Mazumder, Sudhakar M. Reddy. 208-213
• A Module Generator Development Environment: Area Estimation and Design-Space Exploration EncapsulationAkhilesh Tyagi. 214-217
• Area Efficient VLSI Design with Cells of Controllable ComplexityG. Pannerselvam, A. Sarkar, Subir Bandyopadhyay, Graham A. Jullien. 218-221
• A Practical Approach to Layout OptimizationRajeev Govindan, Michael A. Langston, Siddharthan Ramachandramurthi. 222-225
• Performance Aspects of Gate Matrix LayoutBjarne Hald, Jan Madsen. 226-229
• LATCHECK: A Latchup Checker for VLSI LayoutsAditya Agrawal, P. V. Srinivas, G. Sreenivas, Uttiya Dasgupta. 230-235
• Parallel Network Primal-Dual Method on a Shared Memory Multiprocessor and a Unified Approach to VLSI Layout Compaction and Wire BalancingKrishnaiyan Thulasiraman, Prasad R. Chalasani, Parimala Thulasiraman, M. A. Comeau. 242-245
• Architecture of a Min-Max Simulator on MARSKumar N. Lalgudi, Debashis Bhattacharya, Prathima Agrawal. 246-249
• A Massively Parallel, Micro-Grained VLSI ArchitectureRaminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin. 250-255
• MIPS-Driven Early Design and Analysis of VLSI CPU ChipsPradip Bose, John-David Wellman. 256-259
• Modular Design Methodologies for Image Processing ArchitecturesAnna Antola, Alberto Avai, Luca Breveglieri, Andrea Paparella. 260-263
• Export of VLSI Design and CAD: Present and FutureSunil D. Sherlekar. 264
• On Unified Delay Fault TestingAnkan K. Pramanick, Sudhakar M. Reddy. 265-268
• A Path Delay Fault Simulator for Sequential CircuitsSoumitra Bose, Prathima Agrawal, Vishwani D. Agrawal. 269-274
• Synthesis of Sequential Circuits for Robust Path Delay Fault TestabilitySandeep Bhatia, Niraj K. Jha. 275-280
• Delay Fault Test Generation with Cellular AutomataS. Nandi, Vamsi Boppana, Supratik Chakraborty, Parimal Pal Chaudhuri, Samir Roy. 281-286
• An Integrated Technology CAD System for Process and Device DesignersK. S. V. Gopalarao, Uttiya Dasgupta, Rajeev Jain, Duane S. Boning, Purnendu K. Mozumder, V. Chandramouli. 287-292
• A Mechanism for Fine-Grain Concurrent Sharing of Design Data Among CAD ToolsPeter Kist, N. Simon, Mattie Sim, E. Marks, Kees Schot, A. Sarotama. 293-298
• DESSERT: Design Space Exploration of RT Level ComponentsM. V. Rao, M. Balakrishnan, Anshul Kumar. 299-304
• CAE in Requirements Definition and Specification for Complex Microelectronic SystemsKlaus D. Müller-Glaser, J. Bortolazzi, Y. Tanurhan, J. Ernst. 305-310
• Optimizations for Behavioral/RTL SimulationSankaran Karthik, Jacob A. Abraham, Raymond P. Voith. 311-316
• A Shared Memory Parallel Algorithm for Logic SynthesisChieng-Fai Lim, Prithviraj Banerjee, Kaushik De, Saburo Muroga. 317-322
• Minimization of Logic Functions Using Essential Signature SetsPatrick C. McGeer, Jagesh V. Sanghavi, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 323-328
• Towards a Symbolic Logic Minimization AlgorithmOlivier Coudert, Jean Christophe Madre. 329-334
• A Novel Scheme for Synthesis of Easily Testable Finite State Machines Using Cellular AutomataSusanta Misra, Biswadip Mitra, Parimal Pal Chaudhuri. 335-340
• NPCPL: Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput DesignsDebabrata Ghosh, S. K. Nandy, K. Parthasarathy, V. Visvanathan. 341-346
• Fault-Tolerant Arbitration in Multichip Crossbar SwitchesJoydeep Ghosh, Nari Krishnamurthy. 351-356
• High-Speed A/D-D/A Conversion System with Flexible Testing CapabilitiesJoão C. Vital, José E. Franca. 357-362
• A Carry Select Adder with Conflict Free Bypass CircuitM. Shamanna, Sterling R. Whitaker. 363-366