Synthesis of Delay-Verifiable Two-Level Circuits

Wuudiann Ke, Premachandran R. Menon. Synthesis of Delay-Verifiable Two-Level Circuits. In Robert Werner, editor, EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28 - March 3, 1994, Paris, France. pages 297-301, IEEE Computer Society, 1994.

Abstract

Abstract is missing.