Synthesis of Delay-Verifiable Two-Level Circuits

Wuudiann Ke, Premachandran R. Menon. Synthesis of Delay-Verifiable Two-Level Circuits. In Robert Werner, editor, EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28 - March 3, 1994, Paris, France. pages 297-301, IEEE Computer Society, 1994.

@inproceedings{KeM94,
  title = {Synthesis of Delay-Verifiable Two-Level Circuits},
  author = {Wuudiann Ke and Premachandran R. Menon},
  year = {1994},
  researchr = {https://researchr.org/publication/KeM94},
  cites = {0},
  citedby = {0},
  pages = {297-301},
  booktitle = {EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28 - March 3, 1994, Paris, France},
  editor = {Robert Werner},
  publisher = {IEEE Computer Society},
  isbn = {0-8186-5410-4},
}