Abstract is missing.
- Having FUN with Analog TestRobert A. Pease. [doi]
- Computing at the Crossroads (And What Does it Mean to Verification and Test?)Jan N. Rabaey. [doi]
- Managing Test in the End-to-End, Mega Supply ChainMike Lydon. [doi]
- This is a Test: How to Tell if DFT and Test Are Adding Value to Your CompanyJeff Rearick. [doi]
- Production Multivariate Outlier Detection Using Principal ComponentsPeter M. O'Neill. 1-10 [doi]
- Solving In-Circuit Defect Coverage Holes with a Novel Boundary Scan ApplicationDave F. Dubberke, James J. Grealish, Bill Van Dick. 1-9 [doi]
- Deterministic Diagnostic Pattern Generation (DDPG) for Compound DefectsFei Wang, Yu Hu, Huawei Li, Xiaowei Li 0001, Jing Ye, Yu Huang. 1-10 [doi]
- Generating Test Signals for Noise-Based NPR/ACPR Type Tests in ProductionSadok Aouini, Gordon W. Roberts. 1-9 [doi]
- On Accelerating Path Delay Fault Simulation of Long Test SequencesI-De Huang, Yi-Shing Chang, Suriyaprakash Natarajan, Ramesh Sharma, Sandeep K. Gupta. 1-9 [doi]
- Octal-Site EVM Tests for WLAN Transceivers on "Very" Low-Cost ATE PlatformsGanesh Srinivasan, Hui-Chuan Chao, Friedrich Taenzler. 1-9 [doi]
- External Loopback Testing Experiences with High Speed Serial InterfacesAnne Meixner, Akira Kakizawa, Benoit Provost, Serge Bedwani. 1-10 [doi]
- Using Implications for Online Error DetectionKundan Nepal, Nuno Alves, Jennifer Dworak, R. Iris Bahar. 1-10 [doi]
- A New Wafer Level Latent Defect Screening Methodology for Highly Reliable DRAM Using a Response Surface MethodJunghyun Nam, Sunghoon Chun, Gibum Koo, Yanggi Kim, Byungsoo Moon, Jonghyoung Lim, Jaehoon Joo, Sangseok Kang, Hoonjung Kim, Kyeongseon Shin, Kisang Kang, Sungho Kang. 1-10 [doi]
- Test Generation for Interconnect OpensXijiang Lin, Janusz Rajski. 1-7 [doi]
- On-chip Programmable Capture for Accurate Path Delay Test and CharacterizationRajeshwary Tayade, Jacob A. Abraham. 1-10 [doi]
- Parametric Testing of Optical InterfacesBrice Achkir, Pavel Zivny, Bill Eklow. 1 [doi]
- Low Power Scan Shift and Capture in the EDT EnvironmentDariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer. 1-10 [doi]
- SoC Yield Improvement: Redundant Architectures to the Rescue?Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel. 1 [doi]
- DFT Architecture for Automotive Microprocessors using On-Chip Scan Compression supporting Dual Vendor ATPGHeiko Ahrens, Rolf Schlagenhaft, Helmut Lang, V. Srinivasan, Enrico Bruzzano. 1-10 [doi]
- The Test Features of the Quad-Core AMD Opteron- MicroprocessorTim Wood, Grady Giles, Chris Kiszely, Martin Schuessler, Daniela Toneva, Joel Irby, Michael Mateja. 1-10 [doi]
- Reducing Power Supply Noise in Linear-Decompressor-Based Test Data Compression Environment for At-Speed Scan TestingMeng-Fan Wu, Jiun-Lang Huang, Xiaoqing Wen, Kohei Miyase. 1-10 [doi]
- Statistical Yield Modeling for Sub-wavelength LithographyAswin Sreedhar, Sandip Kundu. 1-8 [doi]
- Diagnosis of Logic-to-chain Bridging FaultsWei-Chih Liu, Wei-Lin Tsai, Hsiu-Ting Lin, James Chien-Mo Li. 1 [doi]
- Jitter and Signal Integrity Verification for Synchronous and Asynchronous I/Os at Multiple to 10 GHz/GbpsMike P. Li. 1-6 [doi]
- Power Distribution Failure Analysis Using Transition-Delay Fault PatternsJunxia Ma, Jeremy Lee, Mohammad Tehranipoor. 1 [doi]
- SAT-based State Justification with Adaptive Mining of InvariantsWeixin Wu, Michael S. Hsiao. 1-10 [doi]
- Evaluating the Effectiveness of Physically-Aware N-Detect Test using Real SiliconYen-Tzu Lin, Osei Poku, Ronald D. Blanton, Phil Nigh, Peter Lloyd, Vikram Iyengar. 1-9 [doi]
- DFT Implementationis for Striking the Right Balance between Test Cost and Test Quality for Automotive SOCsAmit Dutta, Srinivasulu Alampally, V. Prasanth, Rubin A. Parekhji. 1-10 [doi]
- Robust Design-for-Productization Practices for High Quality Automotive ProductsPaolo Bernardi, Fabio Melchiori, Davide Pandini, Santo Pugliese, Davide Appello. 1-9 [doi]
- Architecture for Testing Multi-Voltage Domain SOCLaurent Souef, Christophe Eychenne, Emmanuel Alie. 1-10 [doi]
- On-chip Timing Uncertainty Measurements on IBM MicroprocessorsRobert L. Franch, Phillip Restle, James K. Norman, William V. Huott, Joshua Friedrich, R. Dixon, Steve Weitzel, K. van Goor, G. Salem. 1-7 [doi]
- The Advantages of Limiting P1687 to a Restricted SubsetJason Doege, Alfred L. Crouch. 1-8 [doi]
- Hardware Overhead Reduction for Memory BISTMasayuki Arai, Kazuhiko Iwasaki, Michinobu Nakao, Iwao Suzuki. 1 [doi]
- Beyond 10 Gbps? Challenges of Characterizing Future I/O Interfaces with Automated Test EquipmentJose Moreira, Heidi Barnes, Hiroshi Kaga, Michael Comai, Bernhard Roth, Morgan Culver. 1-10 [doi]
- "Plug & Test" at System Level via Testable TLM PrimitivesHoma Alemzadeh, Stefano Di Carlo, Fatemeh Refan, Paolo Prinetto, Zainalabedin Navabi. 1-10 [doi]
- Achieving Zero-Defects for Automotive ApplicationsRajesh Raina. 1-10 [doi]
- Testing Methodology of Embedded DRAMsChi-Min Chang, Mango Chia-Tso Chao, Rei-Fu Huang, Ding-Yuan Chen. 1-9 [doi]
- A History-Based Diagnosis Technique for Static and Dynamic Faults in SRAMsAlexandre Ney, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian. 1-10 [doi]
- On-line Failure Detection in Memory Order BuffersJavier Carretero, Xavier Vera, Pedro Chaparro, Jaume Abella. 1-10 [doi]
- A Low-Cost Programmable Memory BIST Design for Multiple Memory InstancesChung-Fu Lin, Chia-Fu Huang, De-Chung Lu, Chih-Chiang Hsu, Wen-Tsung Chiu, Yu-Wei Chen, Yeong-Jar Chang. 1 [doi]
- Built-in Self-Calibration of On-chip DAC and ADCWei Jiang, Vishwani D. Agrawal. 1-10 [doi]
- Unraveling Variability for Process/Product ImprovementAnne Gattiker. 1-9 [doi]
- rd Generation, 16-core/32-thread UltraSPARC- CMT MicroprocessorIshwar Parulkar, Sriram Anandakumar, Gaurav Agarwal, Gordon Liu, Krishna Rajan, Frank Chiu, Rajesh Pendurkar. 1-10 [doi]
- Hardware-based Error Rate Testing of Digital Baseband Communication SystemsAmirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn. 1-10 [doi]
- Wireless Test Structure for Integrated SystemsZiad Noun, Philippe Cauvet, Marie-Lise Flottes, David Andreu, Serge Bernard. 1 [doi]
- Modeling Test Escape Rate as a Function of Multiple CoveragesKenneth M. Butler, John M. Carulli Jr., Jayashree Saxena. 1-9 [doi]
- Linearity Test Time Reduction for Analog-to-Digital Converters Using the Kalman Filter with Experimental Parameter EstimationLe Jin. 1-8 [doi]
- Test-Access Solutions for Three-Dimensional SOCsXiaoxia Wu, Yibo Chen, Krishnendu Chakrabarty, Yuan Xie. 1 [doi]
- Defect Oriented Testing of the Strap Problem Under Process Variations in DRAMsZaid Al-Ars, Said Hamdioui, A. J. van de Goor, Georg Mueller. 1-10 [doi]
- A Tutorial on STDF Fail Datalog StandardAjay Khoche, Phil Burlison, John Rowe, Glenn Plowman. 1-10 [doi]
- Interconnect-Aware and Layout-Oriented Test-Pattern Selection for Small-Delay DefectsMahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Tehranipoor. 1-10 [doi]
- Testing Techniques for Hardware SecurityMehrdad Majzoobi, Farinaz Koushanfar, Miodrag Potkonjak. 1-10 [doi]
- VLSI Test Exercise Courses for Students in EE DepartmentSatoshi Komatsu. 1 [doi]
- Time-dependent Behaviour of Full Open Defects in Interconnect LinesRosa RodrÃguez-Montañés, Daniel ArumÃ, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman. 1-10 [doi]
- RTL Error Diagnosis Using a Word-Level SAT-SolverSaeed Mirzaeian, Feijun (Frank) Zheng, Kwang-Ting (Tim) Cheng. 1-8 [doi]
- A Novel Pattern Generation Framework for Inducing Maximum Crosstalk Effects on Delay-Sensitive PathsJeremy Lee, Mohammad Tehranipoor. 1-10 [doi]
- Align-Encode: Improving the Encoding Capability of Test Stimulus DecompressorsOzgur Sinanoglu. 1-10 [doi]
- Non-contact Testing for SoC and RCP (SIPs) at Advanced NodesBrian Moore, Marc Mangrum, Chris Sellathamby, Md. Mahbub Reja, T. Weng, Brenda Bai, Edwin Walter Reid, Igor M. Filanovsky, Steven Slupsky. 1-10 [doi]
- A Study of Outlier Analysis Techniques for Delay TestingSean H. Wu, Dragoljub Gagi Drmanac, Li-C. Wang. 1-10 [doi]
- A New Method for Measuring Aperture Jitter in ADC Output and Its Application to ENOB TestingTakahiro J. Yamaguchi, Masayuki Kawabata, Mani Soma, Masahiro Ishida, K. Sawami, Koichiro Uekusa. 1-9 [doi]
- Low cost testing of multi-GBit device pins with ATE assisted loopback instrumentWilliam Fritzsche, Asim E. Haque. 1-8 [doi]
- Analysis of Retention Time Distribution of Embedded DRAM - A New Method to Characterize Across-Chip Threshold Voltage VariationWei Kong, Paul C. Parries, G. Wang, Subramanian S. Iyer. 1-7 [doi]
- Leveraging IEEE 1641 for Tester-Independent ATE SoftwareBethany Van Wagenen, Jon Vollmar, Dan Thornton. 1-10 [doi]
- Justifying DFT with a Hierarchical Top-Down Cost-Benefit ModelScott Davidson. 1-10 [doi]
- Scan Based Testing of Dual/Multi Core Processors for Small Delay DefectsAdit D. Singh. 1-8 [doi]
- On the Correlation between Controller Faults and Instruction-Level Errors in Modern MicroprocessorsNaghmeh Karimi, Michail Maniatakos, Abhijit Jas, Yiorgos Makris. 1-10 [doi]
- An Effective and Flexible Multiple Defect Diagnosis Methodology Using Error Propagation AnalysisXiaochun Yu, Ronald D. Blanton. 1-9 [doi]
- Solder Bead on High Density Interconnect Printed Circuit BoardBrandon Chu. 1-5 [doi]
- Observations of Supply-Voltage-Noise Dispersion in Sub-nsecKan Takeuchi, Genichi Tanaka, Hiroaki Matsushita, Kenichi Yoshizumi, Yusaku Katsuki, Takao Sato. 1-8 [doi]
- A High-Speed Structural Method for Testing Address Decoder Faults in Flash MemoriesOlivier Ginez, Jean Michel Portal, Hassen Aziza. 1-10 [doi]
- IEEE 1500 Compatible Secure Test Wrapper For Embedded IP CoresGeng-Ming Chiu, James Chien-Mo Li. 1 [doi]
- Integration of Hardware Assertions in Systems-on-ChipJeroen Geuzebroek, Bart Vermeulen. 1-10 [doi]
- Test Access Mechanism for Multiple Identical CoresGrady Giles, Jing Wang, Anuja Sehgal, Kedarnath J. Balakrishnan, James Wingfield. 1-10 [doi]
- Detection and Diagnosis of Static Scan Cell Internal DefectRuifeng Guo, Liyang Lai, Yu Huang 0005, Wu-Tung Cheng. 1-10 [doi]
- A Method to Generate a Very Low Distortion, High Frequency Sine Waveform Using an AWGAkinori Maeda. 1-8 [doi]
- Efficiently Performing Yield Enhancements by Identifying Dominant Physical Root Cause from Test Fail DataManish Sharma, Brady Benware, Lei Ling, David Abercrombie, Lincoln Lee, Martin Keim, Huaxing Tang, Wu-Tung Cheng, Ting-Pu Tai, Yi-Jung Chang, Reinhart Lin, Albert Mann. 1-9 [doi]
- Embedded Power Delivery Decoupling in Small Form Factor Test SocketsOmer Vikinski, Shaul Lupo, Gregory Sizikov, Chee Yee Chung. 1-8 [doi]
- Functional Test and Speed/Power Sorting of the IBM POWER6 and Z10 ProcessorsTung N. Pham, Frances Clougherty, Gerard Salem, James M. Crafts, Jon Tetzloff, Pamela Moczygemba, Timothy M. Skergan. 1-7 [doi]
- Increasing Scan Compression by Using X-chainsPeter Wohl, John A. Waicukauski, Frederic Neuveux. 1-10 [doi]
- A Hybrid A/D Converter with 120dB SNR and -125dB THDMamoru Tamba. 1-9 [doi]
- Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim ModelStefan Hillebrecht, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng. 1-10 [doi]
- EVM Testing of Wireless OFDM Transceivers Using Intelligent Back-End Digital Signal Processing AlgorithmsVishwanath Natarajan, Hyun Woo Choi, Deuk Lee, Rajarajan Senguttuvan, Abhijit Chatterjee. 1-10 [doi]
- SOC Test Optimization with Compression-Technique SelectionAnders Larsson, Xin Zhang, Erik Larsson, Krishnendu Chakrabarty. 1 [doi]
- CONCAT: CONflict Driven Learning in ATPG for Industrial designsSurendra Bommu, Kameshwar Chandrasekar, Rahul Kundu, Sanjay Sengupta. 1-10 [doi]
- Fabrication Defects and Fault Models for DNA Self-Assembled NanoelectronicsVincent Mao, Chris Dwyer, Krishnendu Chakrabarty. 1-10 [doi]
- Implementation Update: Logic Mapping On SPARC- MicroprocessorsAnjali Vij, Richard Ratliff. 1-10 [doi]
- Implicit Identification of Non-Robustly Unsensitizable Paths using Bounded Delay ModelDheepakkumaran Jayaraman, Edward Flanigan, Spyros Tragoudas. 1-10 [doi]
- Optical Diagnostics for IBM POWER6- MicroprocessorPeilin Song, Stephen Ippolito, Franco Stellari, John Sylvestri, Tim Diemoz, George Smith, Paul Muench, Norm James, Seongwon Kim, Hector Saenz. 1-9 [doi]
- Optimized Circuit Failure Prediction for Aging: Practicality and PromiseMridul Agarwal, Varsha Balakrishnan, Anshuman Bhuyan, Kyunglok Kim, Bipul C. Paul, Wenping Wang, Bo Yang, Yu Cao, Subhasish Mitra. 1-10 [doi]
- An Efficient Secure Scan Design for an SoC Embedding AES CoreJaehoon Song, Taejin Jung, Junseop Lee, Hyeran Jeong, Byeongjin Kim, Sungju Park. 1 [doi]
- Capture and Shift Toggle Reduction (CASTR) ATPG to Minimize Peak Power Supply NoiseHsiu-Ting Lin, Jen-Yang Wen, James Li, Ming-Tung Chang, Min-Hsiu Tsai, Sheng-Chih Huang, Chili-Mou Tseng. 1 [doi]
- Transition Test on UltraSPARC- T2 MicroprocessorLiang-Chi Chen, Paul Dickinson, Prasad Mantri, Murali M. R. Gala, Peter Dahlgren, Subhra Bhattacharya, Olivier Caty, Kevin Woodling, Thomas A. Ziaja, David Curwen, Wendy Yee, Ellen Su, Guixiang Gu, Tim Nguyen. 1-10 [doi]
- A New Language Approach for IJTAGMichele Portolan, Suresh Goyal, Bradford G. Van Treuren, Chen-Huan Chiang, Tapan J. Chakraborty, Thomas B. Cook. 1-10 [doi]
- VAST: Virtualization-Assisted Concurrent Autonomous Self-TestHiroaki Inoue, Yanjing Li, Subhasish Mitra. 1-10 [doi]
- Distributed Embedded Logic Analysis for Post-Silicon Validation of SOCsHo Fai Ko, Adam B. Kinsman, Nicola Nicolici. 1-10 [doi]
- Launch-on-Shift-Capture Transition TestsIntaik Park, Edward J. McCluskey. 1-9 [doi]
- High Throughput Diagnosis via Compression of Failure Data in Embedded Memory BISTNilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer. 1-10 [doi]
- Engineering Test Coverage on Complex SocketsMyron Schneider, Ayub Shafi. 1-9 [doi]
- Efficient High-Speed Interface Verification and Fault AnalysisThomas Nirmaier, Jose Torres Zaguirre, Eric Liau, Wolfgang Spirkl, Armin Rettenberger, Doris Schmitt-Landsiedel. 1-9 [doi]
- Detection of Internal Stuck-open Faults in Scan ChainsFan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz. 1-10 [doi]
- High Test Quality in Low Pin Count ApplicationsJayant D'Souza, Subramanian Mahadevan, Nilanjan Mukherjee, Graham Rhodes, Jocelyn Moreau, Thomas Droniou, Paul Armagnat, D. Sartoretti. 1 [doi]
- IEEE P1581 drastically simplifies connectivity test for memory devicesHeiko Ehrenberg. 1 [doi]
- Platform Independent Test Access Port ArchitectureArie Margulis, David Akselrod, Tim Wood, Sopho Metsis. 1 [doi]
- Peak Power Reduction Through Dynamic Partitioning of Scan ChainsSobeeh Almukhaizim, Ozgur Sinanoglu. 1-10 [doi]
- Towards a World Without Test Escapes: The Use of Volume Diagnosis to Improve Test QualityStefan Eichenberger, Jeroen Geuzebroek, Camelia Hora, Bram Kruseman, Ananta K. Majhi. 1-10 [doi]
- Improving the Accuracy of Test Compaction through Adaptive Test UpdateSounil Biswas, Ronald D. Blanton. 1 [doi]
- Built-in Self-Test and Fault Diagnosis for Lab-on-Chip Using Digital Microfluidic Logic GatesYang Zhao, Tao Xu, Krishnendu Chakrabarty. 1-10 [doi]
- Is It Cost-Effective to Achieve Very High Fault Coverage for Testing Homogeneous SoCs with Core-Level Redundancy?Lin Huang, Qiang Xu. 1 [doi]
- Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 StandardLaung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Kuen-Jong Lee, Xiaoqing Wen, Wen-Ben Jone, Chia-Hsien Yeh, Wei-Shin Wang, Hao-Jan Chao, Jianghao Guo, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li. 1-9 [doi]
- Augmenting Boundary-Scan Tests for Enhanced Defect CoverageDayton Norrgard, Kenneth P. Parker. 1-8 [doi]
- Problems Using Boundary-Scan for Memory Cluster TestsBradford G. Van Treuren, Chen-Huan Chiang, Kenneth Honaker. 1-10 [doi]
- Bridging the gap between Design and Test Engineering for Functional Pattern DevelopmentErnst Aderholz, Heiko Ahrens, Michael Rohleder. 1-10 [doi]
- SoC Test Architecture Design and Optimization Considering Power Supply Noise EffectsFeng Yuan, Qiang Xu. 1-9 [doi]
- IEEE 1500 Core Wrapper Optimization Techniques and ImplementationBrendan Mullane, Michael Higgins, Ciaran MacNamee. 1-10 [doi]
- Wafer-Level Characterization of Probecards using NAC ProbingGyu-Yeol Kim, Eon-Jo Byunb, Ki-Sang Kang, Young-Hyun Jun, Bai-Sun Kong. 1-9 [doi]
- Boundary-Scan Testing of Power/Ground PinsKenneth P. Parker, Neil G. Jacobson. 1-8 [doi]
- Frequency and Power Correlation between At-Speed Scan and Functional TestsShlomi Sde-Paz, Eyal Salomon. 1-9 [doi]
- An Automatic Post Silicon Clock Tuning System for Improving System Performance based on Tester MeasurementsKelageri Nagaraj, Sandip Kundu. 1-8 [doi]
- Overview of a High Speed Top Side Socket SolutionJohn Stewart, Temitope Animashaun. 1 [doi]
- A Power-Aware Test Methodology for Multi-Supply Multi-Voltage DesignsVivek Chickermane, Patrick R. Gallagher Jr., James Sage, Paul Yuan, Krishna Chakravadhanula. 1-10 [doi]
- Low Power TestSwapnil Bahl, Rajiv Sarkar, Akhil Garg. 1 [doi]
- Failing Frequency Signature AnalysisJaekwang Lee, Edward J. McCluskey. 1-8 [doi]
- Diagnosis of design-silicon timing mismatch with feature encoding and importance ranking - the methodology explainedPouria Bastani, Nicholas Callegari, Li-C. Wang, Magdy S. Abadir. 1-10 [doi]
- Finding Power/Ground Defects on Connectors - Case StudySteve Hird, Reggie Weng. 1-4 [doi]
- Optimized EVM Testing for IEEE 802.11a/n RF ICsErkan Acar, Sule Ozev, Ganesh Srinivasan, Friedrich Taenzler. 1-10 [doi]
- A Shared Parallel Built-In Self-Repair Scheme for Random Access Memories in SOCsTsu-Wei Tseng, Jin-Fu Li. 1-9 [doi]
- Jitters in high performance microprocessorsT. M. Mak. 1-6 [doi]
- Overview of IEEE P1450.6.2 Standard; Creating CTL Model For Memory Test and Repair1 [doi]
- Low Energy On-Line SBST of Embedded ProcessorsAndreas Merentitis, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos. 1-10 [doi]
- Measurement Repeatability for RF Test Within the Load-board Constraints of High Density and Fine Pitch SOC ApplicationsThomas P. Warwick, Gustavo Rivera, David Waite, James Russell, Jeffrey Smith. 1-10 [doi]
- Test Quality Improvement with Timing-aware ATPG: Screening small delay defect case studyChe-Jen Jerry Chang, T. Kobayashi. 1 [doi]
- The Economics of Harm Prevention through Design for TestabilityLouis Y. Ungar. 1-8 [doi]
- Diagnosis of Mask-Effect Multiple Timing Faults in Scan ChainsJing Ye, Fei Wang, Yu Hu, Xiaowei Li 0001. 1 [doi]
- The Importance of Functional-Like Access for Memory TestJonathan Phelps, Chuck Johnson, Corey Goodrich, Aman Kokrady. 1 [doi]
- FPGA Time Measurement Module: Preliminary ResultsWilliam J. Bowhers. 1 [doi]
- Embedded Testing in an In-Circuit Test EnvironmentJohn Malian, Bill Eklow. 1-6 [doi]
- A Generic Framework for Scan Capture Power Reduction in Test Compression EnvironmentXiao Liu, Feng Yuan, Qiang Xu. 1 [doi]
- Design for Test of Asynchronous NULL Convention Logic (NCL) CircuitsWaleed K. Al-Assadi, Sindhu Kakarla. 1-9 [doi]
- System JTAG Initiative Group AdvancementsBradford G. Van Treuren. 1 [doi]
- NoC Reconfiguration for Utilizing the Largest Fault-free Connected Sub-structureArmin Alaghi, Mahshid Sedghi, Naghmeh Karimi, Zainalabedin Navabi. 1 [doi]
- Direct Cell-Stability Test Techniques for an SRAM Macro with Asymmetric Cell-Bias-Voltage ModulationAkira Katayama, Tomoaki Yabe, Osamu Hirabayashi, Yasuhisa Takeyama, Keiichi Kushida, Takahiko Sasaki, Nobuaki Otsuka. 1-7 [doi]
- A Field Analysis of System-level Effects of Soft Errors Occurring in Microprocessors used in Information SystemsSyed Zafar Shazli, Mohammed A. Abdul-Aziz, Mehdi Baradaran Tahoori, David R. Kaeli. 1-10 [doi]
- A Cost Analysis Framework for Multi-core Systems with SparesSaeed Shamshiri, Peter Lisherness, Sung-Jui (Song-Ra) Pan, Kwang-Ting Cheng. 1-8 [doi]
- An Electronic Module for 12.8 Gbps Multiplexing and Loopback TestDavid C. Keezer, Dany Minier, Patrice Ducharme, A. M. Majid. 1-9 [doi]
- Power-Aware At-Speed Scan Test Methodology for Circuits with Synchronous ClocksBenoit Nadeau-Dostie, Kiyoshi Takeshita, Jean-Francois Cote. 1-10 [doi]