Table of Contents

• Embedded Test and Measurement Critical for Deep Submicron TechnologyVinod K. Agarwal. 2 [doi]
• On the Compaction of Test Sets Produced by Genetic OptimizationIrith Pomeranz, Sudhakar M. Reddy. 4-9 [doi]
• On the Adders with Minimum TestsSeiji Kajihara, Tsutomu Sasao. 10-15 [doi]
• Test Generation for Stuck-On Faults in BDD-Based Pass-Transistor Logic SPLTsuyoshi Shinogi, Terumine Hayashi, Kazuo Taki. 16-21 [doi]
• An Algorithmic Test Generation Method for Crosstalk Faults in Synchronous Sequential CircuitsNoriyoshi Itazaki, Yasutaka Idomoto, Kozo Kinoshita. 22 [doi]
• Guaranteeing Testability in Re-encoding for Low PowerSilvia Chiusano, Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda. 30-35 [doi]
• Automatic Testability Analysis of Boards and MCMs at Chip LevelMarc Perbost, Ludovic Le Lan, Christian Landrault. 36-41 [doi]
• Design of C-Testable Multipliers Based on the Modified Booth AlgorithmKwame Osei Boateng, Hiroshi Takahashi, Yuzo Takamatsu. 42-47 [doi]
• Testability Prediction for Sequential Circuits Using Neural NetworkShiyi Xu, Peter Waignjo, Percy G. Dias, Bole Shi. 48 [doi]
• A Genetic Algorithm for the Computation of Initialization Sequences for Synchronous Sequential CircuitsFulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero. 56-61 [doi]
• Sequential Test Generation Based on Circuit Pseudo-TransformationSatoshi Ohtake, Tomoo Inoue, Hideo Fujiwara. 62-67 [doi]
• Exploiting Logic Simulation to Improve Simulation-based Sequential ATPGFulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante. 68-73 [doi]
• TEMPLATES: A Test Generation Procedure for Synchronous Sequential CircuitsIrith Pomeranz, Sudhakar M. Reddy. 74 [doi]
• Design and Implementation of Strongly Code-Disjoint CMOS Built-in Intermediate Voltage Sensor for Totally Self-Checking CircuitsJoseph C. W. Pang, Mike W. T. Wong, Y. S. Lee. 82-87 [doi]
• On fault injection approaches for fault tolerance of feedforward neural networksTakehiro Ito, Itsuo Takanami. 88-93 [doi]
• A concurrent fault-detection scheme for FFT processorsMasahiro Tsunoyama, Masahiko Uenoyama, Tatsuya Kabasawa. 94-99 [doi]
• Code-Disjoint Circuits for Parity CircuitsHendrik Hartje, Michael Gössel, Egor S. Sogomonyan. 100 [doi]
• Testability Features of R10000 MicroprocessorJunji Mori, Ben Mathew, Dave Burns, Yeuk-Hai Mok. 108-111 [doi]
• Application of a Design for Delay Testability Approach to High Speed Logic LSIsKazumi Hatayama, Mitsuji Ikeda, Masahiro Takakura, Satoshi Uchiyama, Yoriyuki Sakamoto. 112-115 [doi]
• An effective fault simulation method for core based LSITakaki Yoshida, Reisuke Shimoda, Takashi Mizokawa, Katsuhiro Hirayama. 116-121 [doi]
• Integrated and Automated Design-for-Testability Implementation for Cell-Based ICsToshinobu Ono, Kazuo Wakui, Hitoshi Hikima, Yoshiyuki Nakamura, Masaaki Yoshida. 122-125 [doi]
• ATREX : Design for Testability System for Mega Gate LSIsMichiaki Emori, Junko Kumagai, Koichi Itaya, Takashi Aikyo, Tomoko Anan, Junichi Niimi. 126 [doi]
• On energy efficiency of VLSI testingCheng-Wen Wu. 132-137 [doi]
• ProTest: A Low Cost Rapid Prototyping Test System for ASICs and FPGAsMarcel Jacomet, Roger Wälti, Lukas Winzenried, Jaime Perez, Martin Gysel. 138-142 [doi]
• Computing stress tests for interconnect defectsVinay Dabholkar, Sreejit Chakravarty. 143-148 [doi]
• Analysis of the Feasibility of Dynamic Thermal Testing in Digital CircuitsJosep Altet, Antonio Rubio, Hideo Tamamoto. 149-154 [doi]
• A test processor chip implementing multiple seed, multiple polynomial linear feedback shift registerZahari M. Darus, Iftekhar Ahmed, Liakot Ali. 155 [doi]
• Automatic EB Fault Tracing System by Successive Circuit Extraction from VLSI CAD Layout DataKatsuyoshi Miura, Kohei Nakata, Koji Nakamae, Hiromu Fujioka. 162-167 [doi]
• An approach to diagnose logical faults in partially observable sequential circuitsKoji Yamazaki, Teruhiko Yamada. 168-173 [doi]
• Guided-Probe Diagnosis of Macro-Cell-Designed LSI CircuitsNorio Kuji. 174 [doi]
• A perturbation based fault modeling and simulation for mixed-signal circuitsNaim Ben Hamida, Khaled Saab, David Marche, Bozena Kaminska. 182-187 [doi]
• Static Testing of ADCs Using Wavelet TransformsTakahiro J. Yamaguchi. 188-193 [doi]
• Analog signal metrology for mixed signal ICsChauchin Su, Yi-Ren Cheng, Yue-Tsang Chen, Shing Tenchen. 194 [doi]
• A New Auto-Focus Method in Critical Dimension Measurement SEMF. Komatsu, H. Motoki, M. Miyoshi. 202-207 [doi]
• Novel Optical Probing System for Quarter-micron VLSI CircuitsK. Ozaki, H. Sekiguchi, S. Wakana, Y. Goto, Y. Umehara, J. Matsumoto. 208-213 [doi]
• New Capabilities of OBIRCH Method for Fault Localization and Defect DetectionKiyoshi Nikawa, Shoji Inoue. 214 [doi]
• On Acceleration of Logic Circuits Optimization Using Implication RelationsHideyuki Ichihara, Kozo Kinoshita. 222-227 [doi]
• A variable reordering method for fast optimization of binary decision diagramsMoonBae Song, Hoon Chang. 228-233 [doi]
• On Decomposition of Kleene TDDsYukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura. 234 [doi]
• Testing for the programming circuit of LUT-based FPGAsHiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Tomoo Inoue, Hideo Fujiwara. 242-247 [doi]
• A XOR-Tree Based Technique for Constant Testability of Configurable FPGAsWei-Kang Huang, M. Y. Zhang, Fred J. Meyer, Fabrizio Lombardi. 248-253 [doi]
• Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGAMichel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian. 254 [doi]
• An Algorithm for All-du-path Testing Coverage of Shared Memory Parallel ProgramsCheer-Sun D. Yang, Lori L. Pollock. 263-268 [doi]
• Estimating the Number of Faults using Simulator based on Generalized Stochastic Petri-Net ModelOsamu Mizuno, Shinji Kusumoto, Tohru Kikuno, Yasunari Takagi, Keishi Sakamoto. 269 [doi]
• On the Complexity of Universal Fault Diagnosis for Look-up Table FPGAsTomoo Inoue, Satoshi Miyazaki, Hideo Fujiwara. 276-281 [doi]
• Fault Diagnosis for Static CMOS CircuitsXiaoqing Wen. 282-287 [doi]
• Fault diagnosis of odd-even sorting networksChih Wei Hu, Chung-Len Lee, Wen Ching Wu, Jwu E. Chen. 288 [doi]
• On The Tradeoff Between Number of Clocks and Number of Latches in Shift RegistersJacob Savir. 296-299 [doi]
• Test Compaction in a Parallel Access Scan EnvironmentSandeep Bhatia, Prab Varma. 300-305 [doi]
• A Partial Scan Design Method Based on n-Fold Line-up StructuresToshinori Hosokawa, Toshihiro Hiraoka, Mitsuyasu Ohta, Michiaki Muraoka, Shigeo Kuninobu. 306 [doi]
• On the capability of delay tests to detect bridges and opensSreejit Chakravarty. 314-319 [doi]
• A Method of Generating Tests for Marginal Delays an Delay Faults in Combinational CircuitsHiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu, Toshiyuki Matsunaga. 320-325 [doi]
• Memory Efficient ATPG for Path Delay FaultsWangning Long, Shiyuan Yang, Zhongcheng Li, Yinghua Min. 326-331 [doi]
• Design of delay-verifiable combinational logic by adding extra inputsXiaoming Yu, Yinghua Min. 332 [doi]
• BIST testability enhancement using high level test synthesis for behavioral and structural designsKowen Lai, Christos A. Papachristou, Mikhail Baklashov. 338-342 [doi]
• On Chip Weighted Random PatternsJacob Savir. 343-352 [doi]
• Random Pattern Testable Design with Partial Circuit DuplicationHiroshi Yokoyama, Xiaoqing Wen, Hideo Tamamoto. 353-358 [doi]
• Accelerated Test Points Selection Method for Scan-Based BISTMichinobu Nakao, Kazumi Hatayama, Isao Higashi. 359 [doi]
• Power supply current monitoring techniques for testing PLLsManeesha Dalmia, André Ivanov, Sassan Tabatabaei. 366-371 [doi]
• Supply Current Test for Unit-to-unit Variations of Electrical Characteristics in GatesMasaki Hashizume, Toshimasa Kuchii, Takeomi Tamesada. 372-377 [doi]
• IDDT TestingYinghua Min, Zhuxing Zhao, Zhongcheng Li. 378-383 [doi]
• Built-in current sensor designs based on the bulk-driven techniqueTsung-Chu Huang, Min-Cheng Huang, Kuen-Jong Lee. 384 [doi]
• Test Length for Random Testing of Sequential Machines Application to RAMsRené David. 392-397 [doi]
• Built-In Self-Test for Multi-Port RAMsYuejian Wu, Sanjay Gupta. 398-403 [doi]
• An extended march test algorithm for embedded memoriesGang-Min Park, Hoon Chang. 404-409 [doi]
• Low Cost Bist for Edac CircuitsDariusz Badura, Andrzej Hlawiczka. 410-415 [doi]