A test processor chip implementing multiple seed, multiple polynomial linear feedback shift register

Zahari M. Darus, Iftekhar Ahmed, Liakot Ali. A test processor chip implementing multiple seed, multiple polynomial linear feedback shift register. In 6th Asian Test Symposium (ATS 97), 17-18 November 1997, Akita, Japan. pages 155, IEEE Computer Society, 1997. [doi]

Abstract

Abstract is missing.