Andrzej Hlawiczka - researchr alias

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Viewing Publication 1 - 23 from 23

2010

How to reduce size of a signature-based diagnostic dictionary used for testing of connectionsTomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka. ddecs 2010: 201-204 [doi]

Reduced-size signature-based diagnostic dictionary for interconnection testingTomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka. pdes 2010: 82-87 [doi]

2009

Effective BIST for crosstalk faults in interconnectsTomasz Rudnicki, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka. ddecs 2009: 164-169 [doi]

2008

Interconnect Faults Identification and Localization Using Modified Ring LFSRsAndrzej Hlawiczka, Krzysztof Gucwa, Tomasz Garbolino, Michal Kopec. ddecs 2008: 247-250 [doi]

2007

Avoiding Crosstalk Influence on Interconnect Delay Fault TestingTomasz Garbolino, Krzysztof Gucwa, Michal Kopec, Andrzej Hlawiczka. ddecs 2007: 149-152

Test Pattern Generator for Delay FaultsTomasz Rudnicki, Andrzej Hlawiczka. ddecs 2007: 255-258

2006

Detection, Localisation and Identification of Interconnection Faults Using MISR CompactorTomasz Garbolino, Michal Kopec, Krzysztof Gucwa, Andrzej Hlawiczka. ddecs 2006: 230-231

Test-per-Clock Detection, Localization and Identification of Interconnect FaultsMichal Kopec, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka. emnets 2006: 233-238 [doi]

2004

Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing CompactorOndrej Novák, Zdenek Plíva, Jiri Nosek, Andrzej Hlawiczka, Tomasz Garbolino, Krzysztof Gucwa. et, 20(1):109-122, 2004. [doi]

2002

Efficient test pattern generators based on specific cellular automata structuresTomasz Garbolino, Andrzej Hlawiczka. mr, 42(6):975-983, 2002. [doi]

Dependable testing of compactor MISR: an imperceptible problem?Andrzej Hlawiczka, Michal Kopec. ets 2002: 31-36 [doi]

2000

Fast and low-area TPGs based on T-type flip-flops can be easily integrated to the scan pathTomasz Garbolino, Andrzej Hlawiczka, Adam Kristof. ets 2000: 161-166 [doi]

Design and testing of fast and cost effective serial seeding TPGs based on one-dimensional linear hybrid cellular automataAndrzej Hlawiczka, Michal Kopec. ats 2000: 380-385 [doi]

1999

A New LFSR with D and T Flip-Flops as an Effective Test Pattern Generator for VLSI CircuitsTomasz Garbolino, Andrzej Hlawiczka. edcc 1999: 321-338 [doi]

1997

Low Cost Bist for Edac CircuitsDariusz Badura, Andrzej Hlawiczka. ats 1997: 410-415 [doi]

A linear code-preserving signature analyzer COPMISRAndrzej Hlawiczka, Michael Gössel, Egor S. Sogomonyan. vts 1997: 350-355 [doi]

1994

Optimized Synthesis of Self-Testable Finite State Machines (FSM) Using BIST-PST Structures in Altera StructuresAndrzej Hlawiczka, Jacek Binda. fpl 1994: 120-122

1992

Parallel Signature Analyzers Using Hybrid Design of Their Linear FeedbacksAndrzej Hlawiczka. TC, 41(12):1562-1571, 1992.

1989

Signature Analysis Testing with Bottom-Top Exclusive Or Type MISRAndrzej Hlawiczka. icftcs 1989: 356-367

1987

Universal Test Controller Chip for Board Self TestAndrzej Hlawiczka, Dariusz Badura. icftcs 1987: 165-175

1986

Compression of Three-State Data Serial Streams by Means of a Parallel LFSR Signature AnalyzerAndrzej Hlawiczka. TC, 35(8):732-741, 1986.

1984

Compression of multiple-valued data serial streams by means of parallel LFSR signature analyzerAndrzej Hlawiczka. icftcs 1984: 404-416

1978

Comments on Procedures for Eliminating Static and Dynamic-Hazards in Test Generation Andrzej Hlawiczka. TC, 27(2):191, 1978.

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