Abstract is missing.
- Silicon technology advances and implications on testGreg Spirakis. 3 [doi]
- A novel test time reduction algorithm for test architecture design for core-based system chipsSandeep Kumar Goel, Erik Jan Marinissen. 7-12 [doi]
- Modeling gate oxide short defects in CMOS minimum transistorsMichel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand. 15-20 [doi]
- ATPG for timing-induced functional errors on trigger events in hardware-software systemsSrikanth Arekapudi, Fei Xin, Jinzheng Peng, Ian G. Harris. 23-28 [doi]
- Dependable testing of compactor MISR: an imperceptible problem?Andrzej Hlawiczka, Michal Kopec. 31-36 [doi]
- RESPIN++ - deterministic embedded testLars Schäfer, Rainer Dorsch, Hans-Joachim Wunderlich. 37-44 [doi]
- Novel ATPG algorithms for transition faultsXiao Liu 0010, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran. 47-52 [doi]
- On selecting testable paths in scan designsYun Shao 0002, Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara. 53-58 [doi]
- Data invalidation analysis for scan-based debug on multiple-clock system chipsSandeep Kumar Goel, Bart Vermeulen. 61-66 [doi]
- System level testing of virtual switch (re-)configuration over IPTiziana Margaria, Oliver Niese, Bernhard Steffen, Andrei Erochok. 67-72 [doi]
- Simulating realistic bridging and crosstalk faults in an industrial settingJonathan Bradford, Hartmut Delong, Ilia Polian, Bernd Becker 0001. 75-80 [doi]
- A real world application used to implement a true IDDQ based test strategy (facts and figures)Hans A. R. Manhaeve, Joseph S. Vaccaro, Loren Benecke, David Prystasz. 81-86 [doi]
- A high accuracy triangle-wave signal generator for on-chip ADC testingSerge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell. 89-94 [doi]
- Investigations for minimum invasion digital only built-in "ramp" based test techniques for charge pump PLL'sMartin John Burbidge, Frédéric Poullet, Jim Tijou, Andrew M. D. Richardson. 95-102 [doi]
- Combining deterministic logic BIST with test point insertionHarald P. E. Vranken, Florian Meister, Hans-Joachim Wunderlich. 105-110 [doi]
- Dynamic test data transformations for average and peak power reductionsOzgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu. 113-118 [doi]
- Power constrained preemptive TAM schedulingErik Larsson, Hideo Fujiwara. 119-126 [doi]