Table of Contents

• New Strategies for System-Level DesignDaniel D. Gajski. 15
• Design and Test of Microfluidic BiochipsKrishnendu Chakrabarty. 17
• Logic Diagnosis and Yield LearningJanusz Rajski. 19
• A Testable Random Bit Generator Based on a High Resolution Phase Noise DetectionMarco Bucci, Raimondo Luzzi. 23-28
• Test Pattern Compression Based on Pattern OverlappingJiri Jenícek, Ondrej Novák. 29-34
• Layout to Logic Defect Analysis for Hierarchical Test GenerationMaksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A. Pleskacz, Michal Rakowski. 35-40
• Design Platform for Quick Integration of an Internet Connectivity into System-on-ChipsBartosz Wojciechowski, Tomasz Kowalczyk, Wojciech Sakowski. 43-48
• Resource Constrained Co-synthesis of Self-reconfigurable SOPCsRadoslaw Czarnecki, Stanislaw Deniziak. 49-54
• Extended Fault Detection Techniques for Systems-on-ChipPaolo Bernardi, Leticia Maria Veiras Bolzani, Matteo Sonza Reorda. 55-60
• A Heuristic for Concurrent SOC Test Scheduling with Compression and SharingAnders Larsson, Erik Larsson, Petru Eles, Zebo Peng. 61-66
• Memories in Scaled Technologies: A Review of Process Induced Failures, Test Methodologies, and Fault ToleranceSaibal Mukhopadhyay, Qikai Chen, Kaushik Roy. 69-74
• Architecture for Highly Reliable Embedded Flash MemoriesBenoît Godard, Jean Michel Daga, Lionel Torres, Gilles Sassatelli. 75-80
• Analysis of Noise Margins Due to Device Parameter Variations in Sub-100nm CMOS TechnologyZhicheng Liang, Makoto Ikeda, Kunihiro Asada. 81-86
• Accurately Determining Bridging Defects from LayoutMaria Gkatziani, Rohit Kapur, Qing Su, Ben Mathew, Roberto Mattiuzzo, Laura Tarantini, Cy Hay, Salvatore Talluto, Thomas W. Williams. 87-90
• FPGA Implementation of Strongly Parallel Histogram EqualizationErnest Jamro, Maciej Wielgosz, Kazimierz Wiatr. 93-98
• Cost-Efficient Synthesis for Sequential Circuits Implemented Using Embedded Memory Blocks of FPGAsGrzegorz Borowik, Bogdan J. Falkowski, Tadeusz Luba. 99-104
• Instruction Memory Architecture Evaluation on Multiprocessor FPGA MPEG-4 EncoderAri Kulmala, Erno Salminen, Timo D. Hämäläinen. 105-110
• A Low Noise and Low Power CMOS Image Sensor with Pixel-level Correlated Double SamplingDongsoo Kim, Gunhee Han. 113-116
• A PMT Interface for the Optical Module Front-end of a Neutrino Underwater TelescopeValeria Sipala, Domenico Lo Presti, Nunzio Randazzo, Luigi Caponetto. 117-120
• A Proposal for ASM++ DiagramsSantiago De Pablo, Santiago Cáceres, Jesús A. Cebrián, Manuel Berrocal. 121-124
• Lightweight Multi-threaded Network Processor Core in FPGAPiotr Buciak, Jakub Botwicz. 125-130
• Parts Obsolescence Challenges for the Electronics IndustryJim Torresen, Thor Arne Lovland. 131-134
• Simulation and Characterization of Wireless Data Acquisition RF Systems for Medical Diagnostic ApplicationKhalil Arshak, Francis Adepoju, Essa Jafer. 135-138
• Two-level Logic Synthesis for Low Power Based on New Model of Power DissipationIreneusz Brzozowski, Andrzej Kos. 139-144
• A March-based Fault Location Algorithm with Partial and Full Diagnosis for All Simple Static Faults in Random Access MemoriesGurgen Harutunyan, Valery A. Vardanian, Yervant Zorian. 145-148
• Avoiding Crosstalk Influence on Interconnect Delay Fault TestingTomasz Garbolino, Krzysztof Gucwa, Michal Kopec, Andrzej Hlawiczka. 149-152
• Instance Generation for SAT-based ATPGDaniel Tille, Görschwin Fey, Rolf Drechsler. 153-156
• Power Testing of an FPGA-based System Using Modelsim Code Coverage CapabilityKhalil Arshak, Essa Jafer, Christian Ibala. 157-160
• XSIM: An Efficient Crosstalk Simulator for Analysis and Modeling of Signal Integrity Faults in Both Defective and Defect-free InterconnectsAjoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier. 161-164
• Built in Defect Prognosis for Embedded MemoriesPrashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani. 167-172
• March CRF: an Efficient Test for Complex Read Faults in SRAM MemoriesLuigi Dilillo, Bashir M. Al-Hashimi. 173-178
• Manifestation of Precharge Faults in High Speed DRAM DevicesZaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev. 179-184
• Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and RepairPhilipp Öhler, Sybille Hellebrand, Hans-Joachim Wunderlich. 185-190
• An Improved MDCT IP Core Generator with Architectural Model SimulationPeter Malík, Marcel Baláz, Tomás Pikula, Martin Simlastík. 193-198
• A Low-Power High-Speed Hybrid CMOS Full Adder for Embedded SystemChiou-Kou Tung, Yu-Cherng Hung, Shao-Hui Shieh, Guo-Shing Huang. 199-202
• Automatic Generation of Circuits for Approximate String MatchingTomás Martínek, Otto Fucík, Patrik Beck, Matej Lexa. 203-208
• About the Efficiency of Real Time Sequences FFT ComputingCostin Cepisca, Sorin Dan Grigorescu, Mircea Covrig, Horia Andrei. 211-214
• Clockless Implementation of LEON2 for Low-Power ApplicationsMartin Simlastík, Viera Stopjaková, Libor Majer, Peter Malík. 215-218
• Decomposition of Logic Functions in Reed-Muller Spectral DomainEdward Hrynkiewicz, Stefan Kolodzinski. 219-222
• Design of Addition and Multiplication Units for High Performance Interval Arithmetic ProcessorAlexandru Amaricai, Mircea Vladutiu, Lucian Prodan, Mihai Udrescu, Oana Boncalo. 223-226
• Establishing a New Course in Reconfigurable Logic System DesignJim Torresen, Jorgen Norendal, Kyrre Glette. 227-230
• Power Dissipation in Basic Global Clock Distribution NetworksArtur L. Sobczyk, Arkadiusz W. Luczyk, Witold A. Pleskacz. 231-234
• Partitioning Optimization by Recursive Moves of Hierarchically Built ClustersRoman Bazylevych, Ihor Podolskyy, Lubov Bazylevych. 235-238
• A Mixed Approach for Unified Logic DiagnosisAlexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel. 239-242
• Design and Analysis of a New Self-Testing Adder which Utilizes Polymorphic GatesLukás Sekanina. 243-246
• A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System ServicesMohammad Hossein Neishaburi, Mohammad Reza Kakoee, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi. 247-250
• Multiple Errors Detection Technique for RAMSergei B. Musin, Alexander A. Ivaniuk, Vyacheslav N. Yarmolik. 251-254
• Test Pattern Generator for Delay FaultsTomasz Rudnicki, Andrzej Hlawiczka. 255-258
• An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening TechniquesOscar Ruano, Pilar Reyes, Juan Antonio Maestro, Luca Sterpone, Pedro Reviriego. 261-266
• A Novel Parity Bit Scheme for SBox in AES CircuitsGiorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. 267-271
• Designing Time-to-Digital Converter for Asynchronous ADCsDariusz Koscielnik, Marek Miskowicz. 275-280
• Algorithm for DRM Signal Recognition in Time Domain and Hardware RealizationLukas Ruckay, Jirí Nedved. 281-286
• RF Transformer Model Parameters MeasurementVytautas Dumbrava, Linas Svilainis. 287-291
• Improving Tolerance to Power-Supply and Temperature Variations in Synchronous CircuitsJorge Semião, J. Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira. 295-300
• A Framework for Self-Healing Radiation-Tolerant Implementations on Reconfigurable FPGAsManuel G. Gericota, Luís F. Lemos, Gustavo R. Alves, José M. Ferreira. 301-306
• Flip-Flops and Scan-Path Elements for NanoelectronicsRené Kothe, Heinrich Theodor Vierhaus. 307-312
• Proposal of VLIW Architecture for Application Specific Processors with Built-in-Self-Repair Facility via Variable Accuracy ArithmeticPawel Pawlowski, Adam Dabrowski, Mario Schölzel. 313-318
• Dedicated Architecture for Double Precision Matrix Multiplication in Supercomputing EnvironmentPawel Russek, Kazimierz Wiatr. 321-324
• Design Issues of a Low Frequency Low-Pass Filter for Medical Applications Using CMOS TechnologyAndrás Timár, Márta Rencz. 325-328
• Feasibility of Image Compression in FPGA-based Neural NetworksVladimir Havel, Karel K. Vlcek. 329-332
• IP Integration Overhead Analysis in System-on-Chip Video EncoderAntti Rasmus, Ari Kulmala, Erno Salminen, Timo D. Hämäläinen. 333-336
• Quadrature-Phase Topology of a High Frequency Ring OscillatorÁbel Vámos. 337-340
• Reticle Exposure Plans for Multi-Project WafersRung-Bin Lin, Da-Wei Hsu, Ming-Hsine Kuo, Meng-Chiou Wu. 341-344
• Low Cost, Low Power, Intelligent Brake Temperature Sensor System for Automotive ApplicationsGyula Bakonyi-Kiss, Zoltán Szucs. 345-348
• Determining MOSFET Parameters in Moderate InversionMatthias Bucher, Antonios Bazigos, Wladyslaw Grabinski. 349-352
• Evolutionary System for Analog Test Frequencies Selection with Fuzzy InitializationTomasz Golonek, Damian Grzechca, Jerzy Rutkowski. 353-356
• Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex SystemPavel Kubalík, Jirí Kvasnicka, Hana Kubatova. 357-360
• Intrusion Detection System Intended for Multigigabit NetworksJan Korenek, Petr Kobierský. 361-364
• Open Defects Caused by Scratches and Yield Modelling in Deep Sub-micron Integrated CircuitWlodzimierz Jonca. 365-368
• Transition Faults Testing Based on Functional Delay TestsEduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas. 371-376
• Redundancy and Test-Pattern Generation for Asynchronous Quasi-Delay-Insensitive Combinational CircuitsAristides Efthymiou. 377-382
• Prototyping Generators for On-line Test Vector Generation Based on PSL PropertiesYann Oddos, Katell Morin-Allory, Dominique Borrione. 383-388
• On Variable Selection in SAT-LP-based Bounded Model Checking of Linear Hybrid AutomataMarc Herbstritt, Bernd Becker, Erika Ábrahám, Christian Herde. 391-396
• SAT-Based Equivalence Checking Based on Circuit Partitioning and Special Approaches for Conflict Clause ReuseFabrício Vivas Andrade, Márcia C. M. Oliveira, Antônio Otávio Fernandes, Claudionor José Nunes Coelho Jr.. 397-402
• Debug Patterns for Efficient High-level SystemC DebuggingFrank Rogin, Erhard Fehlauer, Christian Haufe, Sebastian Ohnewald. 403-408
• Memory Based Analogue Signal Generation Implementation Issues for BISTThomas O. Shea, Ian Grout, Jeffrey Ryan. 411-416
• Developing Virtual ADC Testing Environment in MAPLEPetr Struhovský, Ondrej Subrt, Jirí Hospodka, Pravoslav Martínek. 417-422
• ESD Failures of Integrated Circuits and Their Diagnostics Using Transmission Line PulsingZbigniew Piatek, Jerzy F. Kolodziejski, Witold A. Pleskacz. 423-428
• MEMS Testing by Vibrating CapacitorJanos Mizsei, M. Reggente. 429-432