Ireneusz Brzozowski, Andrzej Kos. Two-level Logic Synthesis for Low Power Based on New Model of Power Dissipation. In Patrick Girard, Andrzej Krasniewski, Elena Gramatová, Adam Pawlak, Tomasz Garbolino, editors, Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), Kraków, Poland, April 11-13, 2007. pages 139-144, IEEE Computer Society, 2007.
Abstract is missing.