Ernest Jamro, Maciej Wielgosz, Kazimierz Wiatr. FPGA Implementation of Strongly Parallel Histogram Equalization. In Patrick Girard, Andrzej Krasniewski, Elena Gramatová, Adam Pawlak, Tomasz Garbolino, editors, Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), Kraków, Poland, April 11-13, 2007. pages 93-98, IEEE Computer Society, 2007.
Abstract is missing.