Abstract is missing.
- Design tools and circuit solutions for degradation-resilient analog circuits in nanometer CMOSGeorges G. E. Gielen. 1 [doi]
- Cognitive self-adaptive computing and communication systems: Test, control and adaptationAbhijit Chatterjee. 2 [doi]
- Challenges for test and design for testAnton Chichkov. 3 [doi]
- An SOC platform for ADC test and measurementBrendan Mullane, Vincent O Brien, Ciaran MacNamee, Thomas Fleischmann. 4-7 [doi]
- A scheme of logic self repair including local interconnectsTobias Koal, Daniel Scheit, Heinrich Theodor Vierhaus. 8-11 [doi]
- Investigating the linearity of MOSFET-only switched-capacitor DeltaSigma modulators under low-voltage conditionFarhad Alibeygi Parsan, Ahmad Ayatollahi, Adib Abrishamifar. 12-15 [doi]
- Comparison of different test strategies on a mixed-signal circuitJuraj Brenkus, Viera Stopjaková, Ronny Vanhooren, Anton Chichkov. 16-19 [doi]
- Case Study : A class E power amplifier for ISO-14443AElke De Mulder, Wim Aerts, Bart Preneel, Ingrid Verbauwhede, Guy Vandenbosch. 20-23 [doi]
- Fast congestion-aware timing-driven placement for island FPGAJinpeng Zhao, Qiang Zhou, Yici Cai. 24-27 [doi]
- Analysis and optimization of ring oscillator using sub-feedback schemeHong-Yi Huang, Fu-Chien Tsai. 28-29 [doi]
- Improve clock gating through power-optimal enable function selectionJuanjuan Chen, Xing Wei, Yunjian Jiang, Qiang Zhou. 30-33 [doi]
- An utilisation of Boolean differential calculus in variables partition calculation for decomposition of logic functionsStefan Kolodzinski, Edward Hrynkiewicz. 34-37 [doi]
- A fast untestability proof for SAT-based ATPGDaniel Tille, Rolf Drechsler. 38-43 [doi]
- The impact of EFSM composition on functional ATPGDavide Bresolin, Giuseppe Di Guglielmo, Franco Fummi, Graziano Pravadelli, Tiziano Villa. 44-49 [doi]
- An efficient fault simulation technique for transition faults in non-scan sequential circuitsAlberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi, Matteo Sonza Reorda. 50-55 [doi]
- Self-timed full adder designs based on hybrid input encodingPadnamabhan Balasubramanian, D. A. Edwards, C. Brej. 56-61 [doi]
- Optimization concepts for self-healing asynchronous circuitsThomas Panhofer, Werner Friesenbichler, Martin Delvai. 62-67 [doi]
- Asynchronous two-level logic of reduced costIgor Lemberski, Petr Fiser. 68-73 [doi]
- Low-voltage low-power double bulk mixer for direct conversion receiver in 65nm CMOSKurt Schweiger, Heimo Uhrmann, Horst Zimmermann. 74-77 [doi]
- Low voltage LNA implementations in 90 nm CMOS technology for multistandard GNSSJacek Gradzki, Tomasz Borejko, Witold A. Pleskacz. 78-83 [doi]
- BIST assisted wideband digital compensation for MB-UWB transmittersShyam Kumar Devarakond, Shreyas Sen, Abhijit Chatterjee. 84-89 [doi]
- Architecture model for approximate palindrome detectionTomás Martínek, Jan Vozenilek, Matej Lexa. 90-95 [doi]
- Packet header analysis and field extraction for multigigabit networksPetr Kobierský, Jan Korenek, Libor Polcak. 96-101 [doi]
- A symbolic RTL synthesis for LUT-based FPGAsStanislaw Deniziak, Mariusz Wisniewski. 102-107 [doi]
- Physical design oriented DRAM Neighborhood Pattern Sensitive Fault testingYiorgos Sfikas, Yiorgos Tsiatouhas. 108-113 [doi]
- Using 3-valued memory representation for state space reduction in embedded assembly code model checkingThomas Reinbacher, Martin Horauer, Bastian Schlich. 114-119 [doi]
- An on-line testing scheme for repairing purposes in Flash memoriesOlivier Ginez, Jean Michel Portal, Hassen Aziza. 120-123 [doi]
- Power devices current monitoring using horizontal and vertical magnetic force sensorMartin Donoval, Martin Daricek, Juraj Marek, Viera Stopjaková. 124-127 [doi]
- Measurement of power supply noise tolerance of self-timed processorKunihiro Asada, Taku Sogabe, Toru Nakura, Makoto Ikeda. 128-131 [doi]
- Test scheme for switched-capacitor circuits by digital analysesYun-Che Wen. 132-135 [doi]
- Structural test of programmed FPGA circuitsMartin Rozkovec, Ondrej Novák. 136-139 [doi]
- Low voltage precharge CMOS logicYngvar Berg, Omid Mirmotahari. 140-143 [doi]
- MDCT / IMDCT low power implementations in 90 nm CMOS technology for MP3 audioPeter Malík, Michal Ufnal, Arkadiusz W. Luczyk, Marcel Baláz, Witold A. Pleskacz. 144-147 [doi]
- Effective mars rover platform design with Hardware / Software co-designGábor Marosy, Zoltán Kovacs, Gyula Horvath. 148-151 [doi]
- On the role of the power supply as an entry for common cause faults - An experimental analysisPeter Tummeltshammer, Andreas Steininger. 152-157 [doi]
- An analysis of the timing behavior of CMOS digital blocks under Simultaneous Switching Noise conditionsFlorence Azaïs, Yves Bertrand, Michel Renovell. 158-163 [doi]
- Effective BIST for crosstalk faults in interconnectsTomasz Rudnicki, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka. 164-169 [doi]
- MTPP - Modular Traffic Processing PlatformJiri Halak, Sven Ubik. 170-173 [doi]
- Simulation and planning method for on-chip power distribution - An industry perspectiveQing K. Zhu, Vincent Bars. 174-177 [doi]
- Experience in Virtual Testing of RSD cyclic A/D convertersMiloslav Kubar, Ondrej Subrt, Pravoslav Martínek, Jiri Jakovenko. 178-181 [doi]
- A 1GHz-GBW operational amplifier for DVB-H receivers in 65nm CMOSHeimo Uhrmann, Franz Schlögl, Kurt Schweiger, Horst Zimmermann. 182-185 [doi]
- 0.5V 160-MHz 260uW all digital phase-locked loopJen-Chieh Liu, Hong-Yi Huang, Wei-Bin Yang, Kuo-Hsing Cheng. 186-193 [doi]
- 0.18 µm CMOS UWB LNA with new feedback configuration for optimization low noise, high gain and small areaY. C. Chang, H. L. Kao, C. H. Kao, C.-H. Yang, Jeffrey S. Fu, Nemai C. Karmakar, L. C. Chang. 194-197 [doi]
- Hardware solution of chaos based image encryptionJiri Giesl, Ladislav Behal, Karel K. Vlcek. 198-201 [doi]
- Diagnosis of faulty units in regular graphs under the PMC modelMiroslav Manik, Elena Gramatová. 202-205 [doi]
- All digital baseband 50 Mbps data recovery using 5× oversampling with 0.9 data unit interval clock jitter toleranceSanad Bushnaq, Toru Nakura, Makoto Ikeda, Kunihiro Asada. 206-209 [doi]
- Contactless characterization of MEMS devices using optical microscopyAndrás Timár, György Bognár. 210-213 [doi]
- A comprehensive approach for soft error tolerant Four State LogicWerner Friesenbichler, Thomas Panhofer, Martin Delvai. 214-217 [doi]
- High-level symbolic simulation for automatic model extractionFlorent Ouchet, Dominique Borrione, Katell Morin-Allory, Laurence Pierre. 218-221 [doi]
- Global parametric faults identification with the use of Differential EvolutionPiotr Jantos, Damian Grzechca, Jerzy Rutkowski. 222-225 [doi]
- Forward and backward guarding in early output logicCharlie Brej, Doug Edwards. 226-229 [doi]
- Logic synthesis method for pattern matching circuits implementation in FPGA with embedded memoriesGrzegorz Borowik, Tadeusz Luba, Bogdan J. Falkowski. 230-233 [doi]
- Contention-avoiding custom topology generation for network-on-chipStanislaw Deniziak, Robert Tomaszewski. 234-237 [doi]
- Enhanced LEON3 core for superscalar processingKrzysztof Marcinek, Arkadiusz W. Luczyk, Witold A. Pleskacz. 238-241 [doi]
- Ultra low-voltage switched current mirrorYngvar Berg, Omid Mirmotahari. 242-245 [doi]
- Self-timed thermal sensing and monitoring of multicore systemsKameswar Rao Vaddina, Ethiopia Nigussie, Pasi Liljeberg, Juha Plosila. 246-251 [doi]
- A CMOS bio-impedance measurement systemAlberto Yufera, Adoración Rueda. 252-257 [doi]
- An enhanced FPGA-based low-cost tester platform exploiting effective test data compression for SoCsL. Ciganda, F. Abate, Paolo Bernardi, M. Bruno, Matteo Sonza Reorda. 258-263 [doi]
- Comprehensive bridging fault diagnosis based on the SLAT paradigmYoussef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Laroussi Bouzaida, Isabelle Izaute. 264-269 [doi]
- Round-level concurrent error detection applied to Advanced Encryption StandardFlavius Opritoiu, Mircea Vladutiu, Mihai Udrescu, Lucian Prodan. 270-275 [doi]