Abstract is missing.
- Bridging the testing speed gap: design for delay testabilityHan Speek, Hans G. Kerkhoff, Manoj Sachdev, Mansour Shashaani. 3-8 [doi]
- Delay fault testing: choosing between random SIC and random MIC test sequencesArnaud Virazel, René David, P. Girard, Christian Landrault, Serge Pravossoudovitch. 9-14 [doi]
- Microprocessor coresAndrew Burdass, Gary Campbell, Richard Grisenthwaite, David Gwilt, Peter Harrod, Richard York. 17-22 [doi]
- System-level test bench generation in a co-design frameworkMarcello Lajolo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Luciano Lavagno. 25-30 [doi]
- LEAP: An accurate defect-free I/sub DDQ/ estimatorAntoni Ferré, Joan Figueras. 33-38 [doi]
- Defect detection from visual abnormalities in manufacturing process using I/sub DDQ/Masaru Sanada. 39-44 [doi]
- Static and dynamic on-chip test response evaluation using a two-mode comparatorDaniela De Venuto, Michael J. Ohletz, G. Matarrese. 47-52 [doi]
- Towards an ADC BIST scheme using the histogram test techniqueFlorence Azaïs, Serge Bernard, Y. Betrand, Michel Renovell. 53-58 [doi]
- A parameterizable fault simulator for bridging faultsPiet Engelke, Bernd Becker 0001, Martin Keim. 63-68 [doi]
- Hierarchical defect-oriented fault simulation for digital circuitsMykola Blyzniuk, T. Cibáková, Elena Gramatová, Wieslaw Kuzmicz, M. Lobur, Witold A. Pleskacz, Jaan Raik, Raimund Ubar. 69-74 [doi]
- Analyzing the test generation problem for an application-oriented test of FPGAsMichel Renovell, Jean Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian. 75-80 [doi]
- Test challenges in nanometer technologiesSandip Kundu, Sanjay Sengupta, Rajesh Galivanche. 83-90 [doi]
- Current testing procedure for deep submicron devicesAnton Chichkov, Dirk Merlier, Peter Cox. 91-96 [doi]
- RTL-based functional test generation for high defects coverage in digital SOCsMarcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira. 99-104 [doi]
- Combining symbolic and genetic techniques for efficient sequential circuit test generationMarco Boschini, Xiaoming Yu, Franco Fummi, Elizabeth M. Rudnick. 105-110 [doi]
- How to avoid random walks in hierarchical test path identificationYiorgos Makris, Jamison Collins, Alex Orailoglu. 111-116 [doi]
- An effective distributed BIST architecture for RAMsMonica Lobetti Bodoni, Alfredo Benso, Silvia Chiusano, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto. 119-124 [doi]
- Compressed bit fail maps for memory fail pattern classificationJörg E. Vollrath, Ulf Lederer, Thomas Hladschik. 125-130 [doi]
- A method for trading off test time, area and fault coverage in datapath BIST synthesisDavid Berthelot, Marie-Lise Flottes, Bruno Rouzeyre. 133-139 [doi]
- Low cost concurrent test implementation for linear digital systemsIsmet Bayraktaroglu, Alex Orailoglu. 140-143 [doi]
- On the use of multiple fault detection times in a method for built-in test pattern generation for synchronous sequential circuitsIrith Pomeranz, Sudhakar M. Reddy. 144-149 [doi]
- A system level boundary scan controller board for VME applications [to CERN experiments]Nuno Cardoso, Carlos Beltrán Almeida, José Carlos da Silva 0001. 153-158 [doi]
- Fast and low-area TPGs based on T-type flip-flops can be easily integrated to the scan pathTomasz Garbolino, Andrzej Hlawiczka, Adam Kristof. 161-166 [doi]
- CA-CSTP: a new BIST architecture for sequential circuitsFulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante. 167-172 [doi]
- Comparison of defect detection capabilities of current-based and voltage-based test methodsBram Kruseman. 175-180 [doi]