Table of Contents

• DFT for High-Quality Low Cost Manufacturing TestJanusz Rajski. 3 [doi]
• Design for Hierarchical Two-Pattern Testability of Data PathsMd. Altaf-Ul-Amin, Satoshi Ohtake, Hideo Fujiwara. 11-16 [doi]
• A Multiple Phase Partial Scan Design MethodDong Xiang, Yi Xu. 17-22 [doi]
• Sequential Redundancy Removal Using Test Generation and Multiple Unreachable StatesHiroyuki Yotsuyanagi, Shinsuke Hata, Masaki Hashizume, Takeomi Tamesada. 23 [doi]
• Tests for Resistive and Capacitive Defects in Address DecodersMatthias Klaus, A. J. van de Goor. 31-36 [doi]
• Detecting Unique Faults in Multi-port SRAMsSaid Hamdioui, A. J. van de Goor, David Eastwick, Mike Rodgers. 37-42 [doi]
• A Memory Specific Notation for Fault ModelingZaid Al-Ars, A. J. van de Goor, Jens Braun, Detlev Richter. 43 [doi]
• On Pass/Fail Dictionaries for Scan Circuits Irith Pomeranz. 51-56 [doi]
• Diagnosis by Repeated Application of Specific Test Inputs and by Output Monitoring of the MISAMichael Gössel, Vitalij Ocheretnij, S. Chakrabarty. 57-62 [doi]
• Simulation-Based Diagnosis for Crosstalk Faults in Sequential CircuitsHiroshi Takahashi, Marong Phadoongsidhi, Yoshinobu Higami, Kewal K. Saluja, Yuzo Takamatsu. 63 [doi]
• Test Generation for Double Stuck-at FaultsYoshinobu Higami, Naoko Takahashi, Yuzo Takamatsu. 71-75 [doi]
• Faulty Resistance Sectioning Technique for Resistive Bridging Fault ATPG SystemsTsuyoshi Shinogi, Tomokazu Kanbayashi, Tomohiro Yoshikawa, Shinji Tsuruoka, Terumine Hayashi. 76-81 [doi]
• On Improving a Fault Simulation Based Test Generator for Synchronous Sequential CircuitsRuifeng Guo, Sudhakar M. Reddy, Irith Pomeranz. 82 [doi]
• Automatic Generation of Memory Built-in Self-Test Cores for System-on-ChipKuo-Liang Cheng, Chia-Ming Hsueh, Jing-Reng Huang, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu. 91-96 [doi]
• A P1500 Compliant BIST-Based Approach to Embedded RAM DiagnosisDavide Appello, Fulvio Corno, M. Giovinetto, Maurizio Rebaudengo, Matteo Sonza Reorda. 97-102 [doi]
• A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM ClustersChih-Wea Wang, Ruey-Shing Tzeng, Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang, Shyh-Horng Lin, Hsin-Po Wang. 103 [doi]
• IDDQ Sensing Technique for High Speed IDDQ TestingTeppei Takeda, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Yukiya Miura, Kozo Kinoshita. 111-116 [doi]
• CMOS Open Defect Detection Based on Supply Current in Time-Variable Electric Field and Supply Voltage ApplicationMasaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada. 117-122 [doi]
• An Approach to Improve the Resolution of Defect-Based DiagnosisIwao Yamazaki, Hiroki Yamanaka, Toshio Ikeda, Masahiro Takakura, Yasuo Sato. 123 [doi]
• A Postprocessing Procedure to Reduce the Number of Different Test Lengths in a Test Set for Scan CircuitsIrith Pomeranz, Sudhakar M. Reddy. 131-136 [doi]
• A Method of Static Compaction of Test StimuliKwame Osei Boateng, Hideaki Konishi, Tsuneo Nakata. 137-144 [doi]
• Dynamic Test Compression Using Statistical CodingHideyuki Ichihara, Atsuhiro Ogawa, Tomoo Inoue, Akio Tamura. 143 [doi]
• Guardband Determination for the Detection of Off-State and Junction Leakages in DRAM TestingMill-Jer Wang, R.-L. Jiang, J.-W. Hsia, Chih-hu Wang, Jwu E. Chen. 151-156 [doi]
• Memory Read Faults: Taxonomy and Automatic Test GenerationAlfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto. 157-163 [doi]
• Simulation and Development of Short Transparent Tests for RAMSerge N. Demidenko, A. J. van de Goor, S. Henderson, P. Knoppers. 164 [doi]
• Test Time Reduction through Minimum Execution of Tester-Hardware Setting InstructionsJunichi Hirase. 173-178 [doi]
• EB-Testing-Pad Method and Its Evaluation by Actual DevicesNorio Kuji, Takako Ishihara. 179-184 [doi]
• Benefits of Phase Interference Detection to IC Waveform ProbingJeffrey A. Block, William K. Lo, Chris Shaw. 185 [doi]
• A DFT Method for Core-Based Systems-on-a-Chip Based on Consecutive TestabilityTomokazu Yoneda, Hideo Fujiwara. 193-198 [doi]
• Compaction Schemes with Minimum Test Application TimeOzgur Sinanoglu, Alex Orailoglu. 199-204 [doi]
• Design of an Optimal Test Access Architecture Using a Genetic AlgorithmZahra Sadat Ebadi, André Ivanov. 205 [doi]
• An RT-Level ATPG Based on Clustering of Circuit StatesHuawei Li, Yinghua Min, Zhongcheng Li. 213-218 [doi]
• An Approach to RTL Fault Extraction and Test GenerationZhigang Yin, Yinghua Min, Xiaowei Li. 219-224 [doi]
• Effective Techniques for High-Level ATPGFulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero. 225 [doi]
• An Efficient Method to Identify Untestable Path Delay FaultsYun Shao, Sudhakar M. Reddy, Seiji Kajihara, Irith Pomeranz. 233-238 [doi]
• SpeedGrade: An RTL Path Delay Fault SimulatorKee Sup Kim, Rathish Jayabharathi, Craig Carstens. 239-243 [doi]
• Test Generation for Multiple-Threshold Gate-Delay Fault ModelMichinobu Nakao, Yoshikazu Kiyoshige, Kazumi Hatayama, Yasuo Sato, Takaharu Nagumo. 244 [doi]
• A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded CoresYannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch. 253-258 [doi]
• Test Scheduling and Scan-Chain Division under Power ConstraintErik Larsson, Zebo Peng. 259-264 [doi]
• Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC DYu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy. 265 [doi]
• A Unified Scheme for Designing Testable State MachinesParag K. Lala, Alvernon Walker. 273-278 [doi]
• Generation of an Ordered Sequence of Test Vectors for Single State Transition Faults in Large Sequential MachinesSamrat Goswami, Anupam Chanda, D. Roy Choudhury. 279-284 [doi]
• Enhancing BIST Quality of Sequential Machines through Degree-of-Freedom AnalysisBiplab K. Sikdar, Samir Roy, Debesh K. Das. 285 [doi]
• Robust Self Concurrent Test of Linear Digital SystemsEmmanuel Simeu, Ahmad Abdelhay, Mohammad A. Naal. 293-298 [doi]
• Control-Flow Checking via Regular ExpressionsAlfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto, Luca Tagliaferri. 299-303 [doi]
• FPGA-Based Fault Injection for Microprocessor SystemsPierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante. 304 [doi]
• BIST Method Based on Concurrent Single-Control Testability of RTL Data PathsKen-ichi Yamaguchi, Hiroki Wada, Toshimitsu Masuzawa, Hideo Fujiwara. 313-318 [doi]
• Faults in Processor Control Subsystems: Testing Correctness and Performance Faults in the Data Prefetching UnitSobeeh Almukhaizim, Peter Petrov, Alex Orailoglu. 319-324 [doi]
• A SmartBIST Variant with Guaranteed EncodingBernd Könemann, Carl Barnhart, Brion L. Keller, Thomas J. Snethen, Owen Farnsworth, Donald L. Wheater. 325 [doi]
• MEMS Comb-Actuator Resonance Measurement Method Using the 2nd Harmonics of the GND CurrentYoshikazu Takahashi. 333-337 [doi]
• On Test and Characterization of Analog Linear Time-Invariant Circuits Using Neural NetworksZhen Guo, Xi Min Zhang, Jacob Savir, Yun-Qing Shi. 338-343 [doi]
• Specification Based Digital Compatible Built-in Test of Embedded Analog CircuitsAchintya Halder, Abhijit Chatterjee. 344 [doi]
• Yield Increase of VLSI after Redundancy-RepairingJunichi Hirase. 353-358 [doi]
• An Improvement in Weight-Fault Tolerance of Feedforward Neural NetworksNaotake Kamiura, Yasuyuki Taniguchi, Teijiro Isokawa, Nobuyuki Matsui. 359-364 [doi]
• A New Code-Disjoint Sum-Bit Duplicated Carry Look-Ahead Adder for Parity CodesVitalij Ocheretnij, Egor S. Sogomonyan, Michael Gössel. 365 [doi]
• Selecting a PRPG: Randomness, Primitiveness, or Sheer Luck?Ismet Bayraktaroglu, Alex Orailoglu. 373-378 [doi]
• Hybrid BIST Using Partially Rotational ScanKenichi Ichino, Takeshi Asakawa, Satoshi Fukumoto, Kazuhiko Iwasaki, Seiji Kajihara. 379-384 [doi]
• Multiple Attractor Cellular Automata for Hierarchical Diagnosis of VLSI CircuitsBiplab K. Sikdar, Niloy Ganguly, Aniket Karmakar, Subha Sankar Chowdhury, Parimal Pal Chaudhuri. 385-390 [doi]
• A Microcode-Based Memory BIST Implementing Modified March AlgorithmDongkyu Youn, Taehyung Kim, Sungju Park. 391-395 [doi]
• Fault Simulation for VHDL Based Test Bench and BIST EvaluationHamed Farshbaf, Mina Zolfy, Shahrzad Mirkhani, Zainalabedin Navabi. 396 [doi]
• Automatic Test Generation for Analog Circuits Using Compact Test Transfer Function ModelsBiranchinath Sahu, Abhijit Chatterjee. 405-410 [doi]
• Distance Constrained Dimensionality Reduction for Parametric Fault Test GeneratorAlfred V. Gomes, Abhijit Chatterjee. 411-416 [doi]
• Short Circuit Faults in State-of-the-Art ADCs - Are They Hard or Soft?A. Lechner, Andrew Richardson, B. Hermes. 417-422 [doi]
• An Embedded Built-in-Self-Test Approach for Digital-to-Analog ConvertersJeng-Horng Tsai, Ming-Jun Hsiao, Tsin-Yuan Chang. 423 [doi]
• An Improved AVPG Algorithm for SoC Design Verification Using Port Order Fault ModelChun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou. 431-436 [doi]
• Framework of Timed Trace Theoretic Verification RevisitedBin Zhou, Tomohiro Yoneda, Chris J. Myers. 437-442 [doi]
• Efficient Pattern-Based Verification of Connections to IP Cores Ilia Polian, Wolfgang Günther, Bernd Becker. 443-448 [doi]
• Design Verification and Robust Design Technique for Cross-Talk FaultsBipul Chandra Paul, Seung Hoon Choi, Yonghee Im, Kaushik Roy. 449 [doi]
• A Practical Logic BIST for ASIC DesignsYasuo Sato, M. Sato, K. Tsutsumida, Toyohito Ikeya, M. Kawashima. 457 [doi]
• Tx7901 DftTetsuo Kamada. 458 [doi]
• An Application of Partial Scan Techniques to a High-End System LSI DesignToshinobu Ono, Akira Kozawa, Takashi Kimura, Yoshihiro Konno, Koji Saga. 459 [doi]
• Built-out Self-Test (BOST) for Analog Circuits in a System LSI: Test Solution to Reduce Test CostsHisayoshi Hanai, Shinji Yamada, Hisaya Mori, Eisaku Yamashita, Teruhiko Funakura. 460 [doi]
• High-Speed Interface TestingM. Suzuki, R. Shimizu, N. Naka, K. Nakamura. 461 [doi]
• A New Inter-Core Built-In-Self-Test Circuits for Tri-State Buffers in the System on a ChipTetsuji Kishi, Mitsuyasu Ohta, Takashi Taniguchi, Hiroshi Kadota. 462 [doi]
• A Flexible Logic BIST Scheme and Its Application to SoC DesignsXiaoqing Wen, Hsin-Po Wang. 463 [doi]
• Experimental Results of Forward-Looking Reverse Order Fault Simulation on Industrial Circuits with ScanIrith Pomeranz, Sudhakar M. Reddy, Xijiang Lin. 467 [doi]
• Non-exhaustive Parity TestingShiyi Xu. 468 [doi]
• Built-in Self-Test for State Faults Induced by Crosstalk in Sequential CircuitsKazuya Shimizu, Noriyoshi Itazaki, Kozo Kinoshita. 469 [doi]
• A Low-Power LFSR ArchitectureTsung-Chu Huang, Kuen-Jong Lee. 470 [doi]