Loïs Guiller - researchr alias

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Viewing Publication 1 - 17 from 17

2006

A Gated Clock Scheme for Low Power Testing of Logic CoresYannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel. et, 22(1):89-99, 2006. [doi]

2004

2003

Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing ConstraintYannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch. itc 2003: 488-493 [doi]

2002

Integrating DFT in the Physical Synthesis FlowLoïs Guiller, Frederic Neuveux, S. Duggirala, R. Chandramouli, Rohit Kapur. itc 2002: 788-795 [doi]

2001

2000

1999

A Test Vector Inhibiting Technique for Low Energy BIST DesignPatrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch. vts 1999: 407-412 [doi]

Circuit Partitioning for Low Power BIST Design with Minimized Peak Power ConsumptionPatrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch. ats 1999: 89-94 [doi]

A Test Vector Ordering Technique for Switching Activity Reduction During Test OperationPatrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch. glvlsi 1999: 24 [doi]

Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activityPatrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Joan Figueras, Salvador Manich, P. Teixeira, M. Santos. iscas 1999: 110-113 [doi]

Low power BIST by filtering non-detecting vectorsSalvador Manich, A. Gabarró, M. Lopez, Joan Figueras, P. Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, P. Teixeira, Marcelino B. Santos. ets 1999: 165-170 [doi]

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