Abstract is missing.
- Validation of a Software Dependability Tool via Fault Injection ExperimentsAlfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Luca Tagliaferri, Paolo Prinetto. 3-8 [doi]
- Exploiting FPGA for Accelerating Fault Injection ExperimentsPierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante. 9-13 [doi]
- Path-Based Error Coverage PredictionJoakim Aidemark, Peter Folkesson, Johan Karlsson. 14-20 [doi]
- Analyzing Fault Effects in Fault Insertion ExperimentsPiotr Gawkowski, Janusz Sosnowski. 21 [doi]
- On-Line BIST and Diagnosis of FPGA Interconnect Using Roving STARsMiron Abramovici, Charles E. Stroud, Matthew Lashinsky, Jeremy Nall, John M. Emmert. 27-33 [doi]
- DRAFT: An On-Line Fault Detection Method for Dynamic and Partially Reconfigurable FPGAsManuel G. Gericota, Gustavo R. Alves, Miguel L. Silva, José M. Ferreira. 34-36 [doi]
- Testing FPGA Delay Faults in the System Environment is Very Different from Ordinary Delay Fault TestingAndrzej Krasniewski. 37 [doi]
- Logic Optimization of Unidirectional Circuits with Structural MethodsLuis Entrena, Celia López, Emilio Olías, Enrique San Millán, José Alberto Espejo. 43-47 [doi]
- Automatic Insertion of Fault-Tolerant Structures at the RT LevelLuis Entrena, Celia López, Emilio Olías. 48-50 [doi]
- On-line Error Detection Techniques for Dependable Embedded Processors with High ComplexityMatthias Pflanz, K. Walther, Heinrich Theodor Vierhaus. 51-53 [doi]
- Novel Fault-Tolerant Adder Design for FPGA-Based SystemsMonica Alderighi, Sergio D Angelo, Giacomo R. Sechi, Cecilia Metra. 54 [doi]
- Logic Insertion to Speed-Up Logic Verification: A Recent DevelopmentDhiraj K. Pradhan. 61-64 [doi]
- Automatic Bias Generation Using Pipeline Instruction State Coverage for Biased Random Instruction GenerationMrinal Bose, Elizabeth M. Rudnick, Magdy S. Abadir. 65 [doi]
- Using a WLFSR to Embed Test Pattern Pairs in Minimum TimeDimitri Kagaris, Spyros Tragoudas. 75-79 [doi]
- A New Reseeding Technique for LFSR-Based Test Pattern GenerationEmmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos. 80-86 [doi]
- A Gated Clock Scheme for Low Power Scan-Based BISTYannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch. 87-89 [doi]
- Test-per-Clock Testing of the Circuits with ScanOndrej Novák, Jiri Nosek. 90 [doi]
- Increasing the Fault Coverage in Multiple Clock Domain Systems by Using On-Line Testing of SynchronizersOctavian Petre, Hans G. Kerkhoff. 95-99 [doi]
- Single Output Distributed Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking ArchitecturesMichele Favalli, Cecilia Metra. 100-105 [doi]
- Concurrent Detection of Soft Errors Based on Current MonitoringY. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos, Costas Efstathiou. 106-110 [doi]
- A New Laser System for X-Rays Flashes Sensitivity EvaluationD. Lewis, Hervé Lapuyade, Yann Deval, Y. Maidon, F. Darracq, R. Briand, Pascal Fouillat. 111 [doi]
- Fault Tolerant Automotive Systems: An OverviewAlberto Manzone, Alessandro Pincetti, Diego De Costantini. 117-121 [doi]
- Smart Temperature Sensor for On-Line Monitoring in Automotive ApplicationsJosé Luis Merino, Sebastià A. Bota, A. Herms, Josep Samitier, Enric Cabruja, X. Jordà, M. Vellvehí, J. Bausells, A. Ferré, J. Bigorr. 122-126 [doi]
- CMOS Differential and Absolute Thermal SensorsAshish Syal, Victor Lee, André Ivanov, Josep Altet. 127 [doi]
- An Approach for Designing On-Line Testable State MachinesParag K. Lala, Mark G. Karpovsky. 135 [doi]
- Power Constrained Test Scheduling with Low Power Weighted Random TestingXiaodong Zhang, Kaushik Roy. 136 [doi]
- Designing Reliable Embedded Systems Based on 32 Bit MicroprocessorsCristiana Bolchini, Fabio Salice, Donatella Sciuto. 137 [doi]
- On-Line Testing in Continuous Operation of Embedded Systems: Modeling and Performance EvaluationChouki Aktouf. 138 [doi]
- Self-Stabilization Testing of LUT-Based FPGA Designs by Fault InjectionMichael Böhnel, Reinhold Weiss. 139 [doi]
- A Study of the Experimental Validation of Fault-Tolerant Systems Using Different VHDL-Based Fault Injection TechniquesJoaquin Gracia, Juan Carlos Baraza, Daniel Gil, Pedro J. Gil. 140 [doi]
- TRACS-TRansient Activity Checking with Scan CellsJose Miguel Vieira dos Santos. 141 [doi]
- An On-Line Testing Approach Using Code-PerturbationZan Yang, Gwan Choi. 142 [doi]
- Fault Tolerant ICs by Area-Optimized Error Correcting CodesRichard P. Kleihorst, Nico F. Benschop. 143 [doi]
- Totally Self-Checking FSM Design Based on Multilevel Synthesis Methods and FPGA ImplemetationA. Matrosova, K. Nikitin, O. Goloubeva. 144 [doi]
- Code-Disjoint Carry-Dependent Sum Adder with Partial Look-AheadVitalij Ocheretnij, Michael Gössel, Egor S. Sogomonyan. 147-152 [doi]
- On the Design of Self-Testing Checkers for Modified Berger CodesStanislaw J. Piestrak, Dimitris Bakalis, Xrysovalantis Kavousianos. 153-157 [doi]
- Fast Configurable Polynomial Division for Error Control Coding ApplicationsFabrice Monteiro, Abbas Dandache, Bernard Lepley. 158 [doi]
- Reliability Properties Assessment at System Level: A Co-design FrameworkCristiana Bolchini, Luigi Pomante, Fabio Salice, Donatella Sciuto. 165-171 [doi]
- Effectiveness and Limitations of Various Software Techniques for Soft Error Detection: A Comparative StudyB. Nicolescu, Raoul Velazco, Matteo Sonza Reorda. 172-177 [doi]
- Supporting Fault Tolerance in an Industrial Environment: The AMATISTA ApproachIsabel González, Luis Berrojo. 178 [doi]
- A New Approach to Design Reliable Real-Time Speech Recognition SystemsFabian Vargas, Rubem Dutra Ribeiro Fagundes, Daniel Barros Jr.. 187-191 [doi]
- Built-In Self Test for Low Cost Testing of a 60 MHz Synchronous Flash MemoryGaetano Palumbo, Giuseppe Introvaia, Vincenzo Mastrocola, Promod Kumar, Francesco Pipiton. 192-196 [doi]
- Design and Test of Certifiable ASICs for Safety-Critical Gas Burners ControFernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira. 197-201 [doi]
- On-Line Multiple-Fault-Detection of Fuzzy ControllersNaotake Kamiura, Teijiro Isokawa, Nobuyuki Matsui, Kazuharu Yamato. 202 [doi]
- A Robust Fault Detection Scheme for Concurrent Testing of Linear Digital SystemsEmmanuel Simeu, Ahmad Abdelhay. 209-214 [doi]
- Fault Diagnosis for Linear Analog Circuits with Symbolic Analysis and Reduced Observable Point SetM. Artioli, F. Filippetti. 215-218 [doi]
- Mixed-Signal Circuit Classification in a Pseudorandom Testing SchemeCristoforo Marzocca, Francesco Corsi. 219 [doi]