Mrinal Bose - researchr alias

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Viewing Publication 1 - 9 from 9

2009

An abstraction mechanism to maximize stimulus portability across RTL, FPGA, software models and silicon of SoCsMrinal Bose, Prashant Naphade, Jayanta Bhadra, Hillel Miller. isqed 2009: 377-381 [doi]

Portable simulation/emulation stimulus on an industrial-strength SoCFrancisco Torres, Rohit Srivastava, Javier Ruiz, Charles H.-P. Wen, Mrinal Bose, Jayanta Bhadra. itc 2009: 1 [doi]

Simulation of a Heterogeneous System at Multiple Levels of Abstraction Using Rendezvous Based ModelingVyas Venkataraman, Di Wang, Wei Qin, Mrinal Bose, Jayanta Bhadra. mtv 2009: 3-8 [doi]

Synthesis Oriented Scheduling of Multiparty Rendezvous in Transaction Level ModelsVyas Venkataraman, Di Wang, Atabak Mahram, Wei Qin, Mrinal Bose, Jayanta Bhadra. isvlsi 2009: 241-246 [doi]

Accelerating multi-party scheduling for transaction-level modelingDi Wang, Vyas Venkataraman, Zhen Wang, Wei Qin, Hangsheng Wang, Mrinal Bose, Jayanta Bhadra. glvlsi 2009: 339-344 [doi]

2003

Modeling IP Responses in Testcase Generation for Systems-on-Chip VerificationMrinal Bose, Mark H. Nodine, William R. Jurasz Jr., Vlad Zavadsky, Arvind Chodavadia, Lincoln R. Nunes. mtv 2003: 7-10 [doi]

2001

Automatic Bias Generation Using Pipeline Instruction State Coverage for Biased Random Instruction GenerationMrinal Bose, Elizabeth M. Rudnick, Magdy S. Abadir. iolts 2001: 65 [doi]

A genetic approach to automatic bias generation for biased random instruction generationMrinal Bose, Jongshin Shin, Elizabeth M. Rudnick, Todd Dukes, Magdy Abadir. cec 2001: 442-448 [doi]

1999

Controlling State Explosion in Static Simulation by Selective CompositionPartha Pratim Chakrabarti, Pallab Dasgupta, Partha Pratim Das, Arnob Roy, Shuvendu K. Lahiri, Mrinal Bose. vlsid 1999: 226-231 [doi]

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