Table of Contents

• Overview of the Scalable Communications Core: A Reconfigurable Wireless Baseband in 65nm CMOSAnthony Chun, Kyle McCanta, Edgar Borrayo Sandoval, Kapil Gulati. 1-6 [doi]
• Reduction of Current Mismatch in PLL Charge PumpH. Md. Shuaeb Fazeel, Leneesh Raghavan, Chandrasekaran Srinivasaraman, Manish Jain. 7-12 [doi]
• Low Phase-Noise and Wide Tuning-Range CMOS Differential VCO for Frequency ?S ModulatorTuan Vu Cao, Dag T. Wisland, Tor Sverre Lande, Farshad Moradi. 13-18 [doi]
• A Low-power Low-cost Optical Router for Optical Networks-on-Chip in Multiprocessor Systems-on-ChipHuaxi Gu, Mo Kwai Hung Morton, Jiang Xu, Wei Zhang. 19-24 [doi]
• High Performance Non-blocking Switch Design in 3D Die-Stacking TechnologyDean L. Lewis, Sudhakar Yalamanchili, Hsien-Hsin S. Lee. 25-30 [doi]
• Leakage Power and Side Channel Security of Nanoscale Cryptosystem-on-Chip (CoC)Amir Khatib Zadeh, Catherine H. Gebotys. 31-36 [doi]
• Context-aware Post Routing Redundant Via InsertionPo-Heng Chu, Rung-Bin Lin, Da-Wei Hsu, Yu-Hsing Chen, Wei-Chiu Tseng. 37-42 [doi]
• Efficient Rerouting Algorithms for Congestion MitigationMohammad Asad R. Chaudhry, Z. Asad, Alexander Sprintson, J. Hu. 43-48 [doi]
• A Non-Uniform Grid Based Ground Plane Model for High Performance Nodes: The Impact of Heterogeneous Cores on Ground Voltage GradientNagarajan Venkateswaran, Ravindhiran Mukundrajan, Mrigank Sharma, Badrinarayanan Ravi. 49-54 [doi]
• On-the-Fly Evaluation of FPGA-Based True Random Number GeneratorRenaud Santoro, Olivier Sentieys, Sébastien Roy. 55-60 [doi]
• Lifetime Reliability Aware Design Flow Techniques for Dual-Vdd Based Platform FPGAsPrasanth Mangalagiri, Vijaykrishnan Narayanan. 61-66 [doi]
• A Self-Reconfigurable Platform for Scalable DCT Computation Using Compressed Partial Bitstreams and BlockRAM PrefetchingJian Huang, Jooheung Lee. 67-72 [doi]
• High-Speed Low-Current Duobinary Signaling Over Active Terminated Chip-to-Chip InterconnectP. Vijaya Sankara Rao, Pradip Mandal, Sunil Sachdev. 73-78 [doi]
• Modern Floorplanning with Boundary Clustering ConstraintLi Li, Yuchun Ma, Ning Xu, Yu Wang, Xianlong Hong. 79-84 [doi]
• An Efficient Hardware Architecture for Multimedia Encryption and Authentication Using the Discrete Wavelet TransformAmit Pande, Joseph Zambreno. 85-90 [doi]
• A New Placement Algorithm for Reduction of Soft Errors in Macrocell Based Design of Nanometer CircuitsKoustav Bhattacharya, Nagarajan Ranganathan. 91-96 [doi]
• Maximally Redundant High-Radix Signed-Digit Adder: New Algorithm and ImplementationSomayeh Timarchi, Keivan Navi, Omid Kavehie. 97-102 [doi]
• Transition Inversion Based Low Power Data Coding Scheme for Synchronous Serial CommunicationAbinesh Ramachandran, Bharghava Rajaram, Mandalika B. Srinivas. 103-108 [doi]
• On-line MPSoC Scheduling Considering Power Gating Induced Power/Ground NoiseYan Xu, Weichen Liu, Yu Wang, Jiang Xu, Xiaoming Chen, Huazhong Yang. 109-114 [doi]
• Hardware Design of the H.264/AVC Variable Block Size Motion Estimation for Real-Time 1080HD Video EncodingRoger Endrigo Carvalho Porto, Luciano Volcan Agostini, Sergio Bampi. 115-120 [doi]
• Dual-Sum Single-Carry Self-Timed Adder DesignsPadmanabhan Balasubramanian, Doug A. Edwards. 121-126 [doi]
• Algorithms for Estimating Number of Glitches and Dynamic Power in CMOS Circuits with Delay VariationsJins D. Alexander, Vishwani D. Agrawal. 127-132 [doi]
• Comparative Analysis of Timing Yield Improvement under Process Variations of Flip-Flops CircuitsHassan Mostafa, Mohab Anis, Mohamed I. Elmasry. 133-138 [doi]
• Testing Circuit-Partitioned 3D IC DesignsDean L. Lewis, Hsien-Hsin S. Lee. 139-144 [doi]
• Dynamic Reconfiguration of Two-Level Caches in Soft Real-Time Embedded SystemsWeixun Wang, Prabhat Mishra. 145-150 [doi]
• Scheduling for an Embedded Architecture with a Flexible DatapathThomas Schilling, Magnus Själander, Per Larsson-Edefors. 151-156 [doi]
• Mapping Data and Code into Scratchpads from Relocatable BinariesAlexandre K. I. Mendonça, Daniel P. Volpato, José Luís Güntzel, Luiz C. V. dos Santos. 157-162 [doi]
• Lossless Compression Using Efficient Encoding of BitmasksChetan Murthy, Prabhat Mishra. 163-168 [doi]
• Secure Leakage-Proof Public Verification of IP Marks in VLSI Physical DesignDebasri Saha, Susmita Sur-Kolay. 169-174 [doi]
• Synchronization-Based Abstraction Refinement for Modular Verification of Asynchronous DesignsHao Zheng 0001, Haiqiong Yao, Tomohiro Yoneda. 175-180 [doi]
• An Analytical Model to Study Optimal Area Breakdown between Cores and Caches in a Chip MultiprocessorTaecheol Oh, Hyunjin Lee, Kiyeon Lee, Sangyeun Cho. 181-186 [doi]
• Inducing Thermal-Awareness in Multicore Systems Using Networks-on-ChipDavid Atienza, Emilio Martinez. 187-192 [doi]
• A Novel Low Area Overhead Body Bias FPGA Architecture for Low Power ApplicationsSungmin Bae, Krishnan Ramakrishnan, Narayanan Vijaykrishnan. 193-198 [doi]
• High Speed Parallel Architecture for Cyclic Convolution Based on FNTJian Zhang, Shuguo Li. 199-204 [doi]
• A High-Speed GCD Chip: A Case Study in Asynchronous DesignGennette Gill, John Hansen, Ankur Agiwal, Leandra Vicci, Montek Singh. 205-210 [doi]
• A High Performance Unified BCD and Binary Adder/SubtractorAnshul Singh, Aman Gupta, Sreehari Veeramachaneni, M. B. Srinivas. 211-216 [doi]
• Thermal-Assisted Spin Transfer Torque Memory (STT-RAM) Cell Design ExplorationHai Li, Haiwen Xi, Yiran Chen, John Stricklin, XiaoBin Wang, Tong Zhang. 217-222 [doi]
• The Ternary Quantum-dot Cellular Automata Memorizing CellPrimoz Pecar, Miha Janez, Nikolaj Zimic, Miha Mraz, Iztok Lebar Bajec. 223-228 [doi]
• Design of Efficient Reversible Binary Subtractors Based on a New Reversible GateHimanshu Thapliyal, Nagarajan Ranganathan. 229-234 [doi]
• NoC Power Optimization Using a Reconfigurable RouterCaroline Concatto, Debora Matos, Luigi Carro, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin, Márcio Eduardo Kreutz. 235-240 [doi]
• Synthesis Oriented Scheduling of Multiparty Rendezvous in Transaction Level ModelsVyas Venkataraman, Di Wang, Atabak Mahram, Wei Qin, Mrinal Bose, Jayanta Bhadra. 241-246 [doi]
• Power-Efficient Body-Coupled Self-Cascode LC Oscillator for Low-Power Injection-Locked Transmitter ApplicationsMohammad Rafiqul Haider, Syed Kamrul Islam. 247-251 [doi]
• Energy-Efficient Encoding for High-Performance Buses with Staggered RepeatersSharath Jayaprakash, Nihar R. Mahapatra. 252-257 [doi]
• All Digital Duty Cycle Correction Circuit in 90nm Based on MutexSwathi Ramasahayam, M. B. Srinivas. 258-262 [doi]
• A Process Variation Tolerant Self-Compensating Sense Amplifier DesignAarti Choudhary, Sandip Kundu. 263-267 [doi]
• An 8-bit 1.8 V 500 MSPS CMOS Segmented Current Steering DACSantanu Sarkar 0002, Swapna Banerjee. 268-273 [doi]
• Floorplan Driven High Level Synthesis for Crosstalk Noise Minimization in Macro-cell Based DesignsHariharan Sankaran, Srinivas Katkoori. 274-279 [doi]
• Low Cost and Memoryless CAVLD Architecture for H.264/AVC DecoderThaísa Leal da Silva, João Alberto Vortmann, Luciano Volcan Agostini, Altamiro Amadeu Susin, Sergio Bampi. 280-285 [doi]
• TEPS: Transient Error Protection Utilizing Sub-word ParallelismSeokin Hong, Soontae Kim. 286-291 [doi]
• A Low Cost Low Power Quaternary LUT Cell for Fault Tolerant Applications in Future TechnologiesEduardo Luis Rhod, Luigi Carro. 292-297 [doi]
• Variation Aware Routing for Three-Dimensional FPGAsChen Dong, Scott Chilstedt, Deming Chen. 298-303 [doi]
• Increasing the Sensitivity of On-Chip Digital Thermal Sensors with Pre-FilteringZhimin Chen, Raghunandan Nagesh, Anand Reddy, Patrick Schaumont. 304-309 [doi]