Table of Contents

• A2DTest: A complete integrated solution for on-chip ADC self-test and analysisBrendan Mullane, Vincent O'Brien, Ciaran MacNamee, Thomas Fleischmann. 1-10 [doi]
• IEEE P1687 IJTAG a presentation of current technologyKen Posse, Al Crouch, Jeff Rearick. 1 [doi]
• A development platform and electronic modules for automated test up to 20 GbpsDavid C. Keezer, Carl Gray, A. M. Majid, Dany Minier, Patrice Ducharme. 1-11 [doi]
• SSC applied serial ATA signal generation and analysis by analog tester resourcesHideo Okawara. 1-9 [doi]
• Test infrastructures evaluation at transaction levelStefano Di Carlo, Nadereh Hatami, Paolo Prinetto. 1 [doi]
• Portable simulation/emulation stimulus on an industrial-strength SoCFrancisco Torres, Rohit Srivastava, Javier Ruiz, Charles H.-P. Wen, Mrinal Bose, Jayanta Bhadra. 1 [doi]
• A novel architecture for on-chip path delay measurementXiaoxiao Wang, Mohammad Tehranipoor, Ramyanshu Datta. 1-10 [doi]
• Compression based on deterministic vector clustering of incompatible test cubesGrzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer. 1-10 [doi]
• Eliminating product infant mortality failures using prognostic analysisLen Losik. 1 [doi]
• Built-in Self Test for Error Vector Magnitude measurement of RF transceiverBilal El Kassir, Christophe Kelma, Bernard Jarry, Michel Campovecchio. 1 [doi]
• Compression-aware pseudo-functional testingFeng Yuan, Qiang Xu. 1-10 [doi]
• Test economics for homogeneous manycore systemsLin Huang, Qiang Xu. 1-10 [doi]
• On simultaneous shift- and capture-power reduction in linear decompressor-based test compression environmentXiao Liu, Qiang Xu. 1-10 [doi]
• ® IBIST, the full vision realizedJay J. Nejedlo, Rahul Khanna. 1-11 [doi]
• Cache-resident self-testing for I/O circuitryS. Gurumurthy, D. Bertanzetti, P. Jakobsen, Jeff Rearick. 1-8 [doi]
• Test access mechanism for multiple identical coresGrady Giles, Jing Wang, Anuja Sehgal, Kedarnath J. Balakrishnan, James Wingfield. 1-10 [doi]
• Speeding up bounded sequential equivalence checking with cross-timeframe state-pair constraints from data learningChia-Ling Chang, Charles H.-P. Wen, Jayanta Bhadra. 1-8 [doi]
• Built-in EVM measurement for OFDM transceivers using all-digital DFTEnder Yilmaz, Afsaneh Nassery, Sule Ozev, Erkan Acar. 1-10 [doi]
• On-chip power supply noise measurement using Time Resolved Emission (TRE) waveforms of Light Emission from Off-State Leakage Current (LEOSLC)Franco Stellari, Peilin Song, John Sylvestri, D. Miles, Orazio P. Forlenza, Donato O. Forlenza. 1-10 [doi]
• Augmenting board test coverage with new intel powered opens boundary scan instructionChwee Liong Tee, Tzyy Haw Tan, Chin Chuan Ng. 1-10 [doi]
• Physical defect modeling for fault insertion in system reliability testZhaobo Zhang, Zhanglei Wang, Xinli Gu, Krishnendu Chakrabarty. 1-10 [doi]
• Testing bridges to nowhere - combining Boundary Scan and capacitive sensingSteve Sunter, Kenneth P. Parker. 1-10 [doi]
• Cost-effective approach to improve EMI yield lossHsuan-Chung Ko, Deng-Yao Chang, Cheng-Nan Hu. 1-8 [doi]
• Very-Low-Voltage testing of amorphous silicon TFT circuitsShiue-Tsung Shen, Wei-Hsiao Liu, Chien-Mo James Li, I-Chun Cheng. 1 [doi]
• Manufacturing data: Maximizing value using component-to-system analysisMatthias Kamm. 1 [doi]
• Power and thermal constrained test schedulingChunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan. 1 [doi]
• Voltage transient detection and induction for debug and testRex Petersen, Pankaj Pant, Pablo Lopez, Aaron Barton, Jim Ignowski, Doug Josephson. 1-10 [doi]
• TM T2 familyLiang-Chi Chen, Paul Dickinson, Peter Dahlgren, Scott Davidson, Olivier Caty, Kevin Wu. 1-10 [doi]
• Enabling GSM/GPRS/EDGE EVM testing on low cost multi-site testersBobby Lai, Chris Rivera, Khurram Waheed. 1-7 [doi]
• AutoRex: An automated post-silicon clock tuning toolDesta Tadesse, Joel Grodstein, R. Iris Bahar. 1-10 [doi]
• An economical, precise and limited access In-Circuit Test method for pulse-width modulation (PWM) circuitsAlbert Yeh, Jesse Chou, Max Lin. 1-9 [doi]
• NAND flash testing: A preliminary study on actual defectsPierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard. 1 [doi]
• A novel test flow for one-time-programming applications of NROM technologyChing-Yu Chin, Yao-Te Tsou, Chi-Min Chang, Mango Chia-Tso Chao. 1-9 [doi]
• Diagnostic test generation for transition faults using a stuck-at ATPG toolYoshinobu Higami, Yosuke Kurose, Satoshi Ohno, Hironori Yamaoka, Hiroshi Takahashi, Yoshihiro Shimizu, Takashi Aikyo, Yuzo Takamatsu. 1-9 [doi]
• Trace signal selection for debugging electrical errors in post-silicon validationXiao Liu, Qiang Xu. 1 [doi]
• New modeling methods for bounded Gaussian jitter (BGJ)/noise (BGN) and their applications in jitter/noise estimation/testingMasashi Shimanouchi, Mike P. Li, Daniel Chow. 1-8 [doi]
• Comparing the effectiveness of deterministic bridge fault and multiple-detect stuck fault patterns for physical bridge defects: A simulation and silicon studySandeep Kumar Goel, Narendra Devta-Prasanna, Mark Ward. 1-10 [doi]
• Application of non-parametric statistics of the parametric response for defect diagnosisRama Gudavalli, W. Robert Daasch, Phil Nigh, Douglas Heaberlin. 1-10 [doi]
• Data learning techniques and methodology for Fmax predictionJanine Chen, Li-C. Wang, Po-Hsien Chang, Jing Zeng, S. Yu, Michael Mateja. 1-10 [doi]
• Low cost AM/AM and AM/PM distortion measurement using distortion-to-amplitude transformationsShreyas Sen, Shyam Kumar Devarakond, Abhijit Chatterjee. 1-10 [doi]
• High Speed I/O Test Cable Assembly Interfaces for Next Generation Multi-Gigabit Serial ProtocolsJim Vana, Alexander Barr, Richard Scherer, Abhay Joshi. 1 [doi]
• Microprocessor system failures debug and fault isolation methodologyEnamul Amyeen, Srikanth Venkataraman, Mun Wai Mak. 1-10 [doi]
• Design for failure analysis inserting replacement-type observation points for LVPJunpei Nonaka, Toshio Ishiyama, Kazuki Shigeta. 1-10 [doi]
• A comprehensive TCAM test scheme: An optimized test algorithm considering physical layout and combining scan test with at-speed BIST designHsiang-Huang Wu, Jih-Nung Lee, Ming-Cheng Chiang, Po-Wei Liu, Chi-Feng Wu. 1-10 [doi]
• Test effectiveness evaluation through analysis of readily-available tester dataYen-Tzu Lin, Ronald D. Blanton. 1-10 [doi]
• A robust method for identifying a deterministic jitter model in a total jitter distributionTakahiro J. Yamaguchi, Kiyotaka Ichiyama, X. H. Hou, Masahiro Ishida. 1-10 [doi]
• BIST scheme for RF VCOs allowing the self-correction of the cutLuca Testa, Hervé Lapuyade, Yann Deval, Olivier Mazouffre, Jean-Louis Carbonéro, Jean-Baptiste Begueret. 1-10 [doi]
• Fast circuit topology based method to configure the scan chains in Illinois Scan architectureSwapneel Donglikar, Mainak Banga, Maheshwar Chandrasekar, Michael S. Hsiao. 1-10 [doi]
• Automatic diagnostic tool for Analog-Mixed Signal and RF load boardsSukeshwar Kannan, Bruce C. Kim. 1 [doi]
• Tolerance of performance degrading faults for effective yield improvementTong-Yu Hsieh, Melvin A. Breuer, Murali Annavaram, Sandeep K. Gupta, Kuen-Jong Lee. 1-10 [doi]
• Minimizing outlier delay test cost in the presence of systematic variabilityDragoljub Gagi Drmanac, Brendon Bolin, Li-C. Wang, Magdy S. Abadir. 1-10 [doi]
• What is IEEE P1149.8.1 and why?Kenneth P. Parker, Jeff Burgess. 1 [doi]
• An outlier detection based approach for PCB testingXin He, Yashwant K. Malaiya, Anura P. Jayasumana, Kenneth P. Parker, Stephen Hird. 1-10 [doi]
• An ant colony optimization technique for abstraction-guided state justificationMin Li, Michael S. Hsiao. 1-10 [doi]
• Feature based similarity search with application to speedpath analysisNicholas Callegari, Li-C. Wang, Pouria Bastani. 1-10 [doi]
• A timestamping method using reduced cost ADC hardwareTimothy Daniel Lyons. 1-8 [doi]
• Design-for-secure-test for crypto coresYouhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki. 1 [doi]
• X-alignment techniques for improving the observability of response compactorsOzgur Sinanoglu, Sobeeh Almukhaizim. 1-10 [doi]
• Test point insertion using functional flip-flops to drive control pointsJoon-Sung Yang, Benoit Nadeau-Dostie, Nur A. Touba. 1-10 [doi]
• Running scan test on three pins: yes we can!Jocelyn Moreau, Thomas Droniou, Philippe Lebourg, Paul Armagnat. 1-10 [doi]
• Boundary-scan adoption - an industry snapshot with emphasis on the semiconductor industryPhilip B. Geiger, Steve Butkovich. 1-10 [doi]
• Capture power reduction using clock gating aware test generationKrishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Prashant Narang. 1-9 [doi]
• Doing more with less - An IEEE 1149.7 embedded tutorial : Standard for reduced-pin and enhanced-functionality test access port and boundary-scan architectureAdam W. Ley. 1-10 [doi]
• Test Mode Entry and Exit Methods for IEEE P1581 compliant devicesHeiko Ehrenberg. 1 [doi]
• A novel array-based test methodology for local process variation monitoringTseng-Chin Luo, Mango Chia-Tso Chao, Michael S.-Y. Wu, Kuo-Tsai Li, Chin C. Hsia, Huan-Chi Tseng, Chuen-Uan Huang, Yuan-Yao Chang, Samuel C. Pan, Konrad K.-L. Young. 1-9 [doi]
• Low cost test point insertion without using extra registers for high performance designHaoxing Ren, Mary P. Kusko, Victor N. Kravets, Rona Yaari. 1-8 [doi]
• Defect-oriented cell-aware ATPG and fault simulation for industrial cell libraries and designsFriedrich Hapke, Rene Krenz-Baath, Andreas Glowatz, Jürgen Schlöffel, Hamidreza Hashempour, Stefan Eichenberger, Camelia Hora, Dan Adolfsson. 1-10 [doi]
• Fast extended test access via JTAG and FPGAsSergei Devadze, Artur Jutman, Igor Aleksejev, Raimund Ubar. 1-7 [doi]
• Accurate measurement of small delay defect coverage of test patternsNarendra Devta-Prasanna, Sandeep Kumar Goel, Arun Gunda, Mark Ward, P. Krishnamurthy. 1-10 [doi]
• Fine resolution double edge clipping with calibration technique for built-in at-speed delay testingChen-I Chung, Shuo-Wen Chang, Ching-Hwa Cheng. 1 [doi]
• Thermal characterization of BIST, scan design and sequential test methodologiesMuzaffer O. Simsir, Niraj K. Jha. 1-9 [doi]
• Fault diagnosis for embedded read-only memoriesNilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer. 1-10 [doi]
• Testing 3D chips containing through-silicon viasErik Jan Marinissen, Yervant Zorian. 1-11 [doi]
• Non-invasive RF built-in testing using on-chip temperature sensorsEduardo Aldrete-Vidrio, Marvin Onabajo, Josep Altet, Diego Mateo, José Silva-Martínez. 1 [doi]
• Scalable and efficient integrated test architectureMichele Portolan, Suresh Goyal, Bradford G. Van Treuren. 1 [doi]
• Defect coverage of non-intrusive board tests (NBT): What does it mean when a non-intrusive board test passes?Adam W. Ley. 1 [doi]
• Dynamic arbitrary jitter injection method for ≫6.5Gb/s SerDes testingTasuku Fujibe, Masakatsu Suda, Kazuhiro Yamamoto, Yoshihito Nagata, Kazuhiro Fujita, Daisuke Watanabe, Toshiyuki Okayasu. 1-10 [doi]
• Power scan: DFT for power switches in VLSI designsBing-Chuan Bai, Chien-Mo James Li, Augusli Kifli, Even Tsai, Kun-Cheng Wu. 1 [doi]
• Low power multi-chains encoding scheme for SoC in low-cost environmentPo-Han Wu, Jiann-Chyi Rau. 1 [doi]
• A novel multisite testing techniques by using frequency synthesizerBoyon Kim, Il-Chan Park, Giseob Song, Wooseong Choi, Byeong-Yun Kim, Kyutaek Lee, Chi-young Choi. 1 [doi]
• An industrial case study for X-canceling MISRJoon-Sung Yang, Nur A. Touba, Shih-yu Yang, T. M. Mak. 1-10 [doi]