Yi-Min Jiang - researchr alias

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Viewing Publication 1 - 21 from 21

2022

Congestion and Timing Aware Macro Placement Using Machine Learning Predictions from Different Data Sources: Cross-design Model Applicability and the Discerning EnsembleXiang Gao, Yi-Min Jiang, Lixin Shao, Pedja Raspopovic, Menno E. Verbeek, Manish Sharma, Vineet Rashingkar, Amit Jalota. ispd 2022: 195-202 [doi]

2014

A method of batching conflict routings in shuffle-exchange networksYi-Hao Zhang, Yue-hong Shen, Min Dong, Yi-Min Jiang. TCS, 522:24-33, 2014. [doi]

2008

Simultaneous Sleep Transistor Insertion and Power Network Synthesis for Industrial Power Gating DesignsKaijian Shi, Zhian Lin, Yi-Min Jiang, Lin Yuan. jcp, 3(3):6-13, 2008. [doi]

2007

A Power Network Synthesis Method for Industrial Power Gating DesignsKaijian Shi, Zhian Lin, Yi-Min Jiang. isqed 2007: 362-367 [doi]

2003

Modeling, testing, and analysis for delay defects and noise effects in deep submicron devicesJing-Jia Liou, Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng. tcad, 22(6):756-769, 2003. [doi]

2001

2000

Estimation for maximum instantaneous current through supply lines for CMOS circuitsYi-Min Jiang, Angela Krstic, Kwang-Ting Cheng. tvlsi, 8(1):61-73, 2000. [doi]

Dynamic Timing Analysis Considering Power Supply Noise EffectsYi-Min Jiang, Angela Krstic, Kwang-Ting Cheng. isqed 2000: 137-144 [doi]

Path Selection and Pattern Generation for Dynamic Timing Analysis Considering Power Supply Noise EffectsJing-Jia Liou, Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng. iccad 2000: 493-496

1999

Analysis of Performance Impact Caused by Power Supply Noise in Deep Submicron DevicesYi-Min Jiang, Kwang-Ting Cheng. dac 1999: 760-765 [doi]

VIP - an input pattern generator for indentifying critical voltage drop for deep sub-micron designsYi-Min Jiang, Tak K. Young, Kwang-Ting Cheng. islped 1999: 156-161 [doi]

Delay testing considering power supply noise effectsYi-Min Jiang, Angela Krstic, Kwang-Ting Cheng. itc 1999: 181-190

1998

Estimation of maximum power supply noise for deep sub-micron designsYi-Min Jiang, Kwang-Ting Cheng, An-Chang Deng. islped 1998: 233-238 [doi]

Exact and Approximate Estimation for Maximum Instantaneous Current of CMOS CircuitsYi-Min Jiang, Kwang-Ting Cheng. date 1998: 698 [doi]

A Hybrid Power Model for RTL Power EstimationYi-Min Jiang, Shi-Yu Huang, Kwang-Ting Cheng, Deborah C. Wang, ChingYen Ho. aspdac 1998: 551-556

1997

Post-Layout Logic Restructuring for Performance OptimizationYi-Min Jiang, Angela Krstic, Kwang-Ting Cheng, Malgorzata Marek-Sadowska. dac 1997: 662-665 [doi]

1994

Performance-driven interconnection optimization for microarchitecture synthesisYi-Min Jiang, Tsing-Fa Lee, TingTing Hwang, Youn-Long Lin. tcad, 13(2):137-149, 1994. [doi]

1992

Performance-driven interconnection optimization for microarchitecture synthesisYi-Min Jiang, Tsing-Fa Lee, TingTing Hwang, Yaun-Long Lin. eurodac 1992: 118-123 [doi]

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