Abstract is missing.
- High performance DSPs - what s hot and what s not?Bryan D. Ackland, Chris Nicol. 1-6 [doi]
- Low power and low voltage CMOS digital circuit techniquesChrister Svensson, Atila Alvandpour. 7-10 [doi]
- CMOS front end components for micropower RF wireless systemsTsung-Hsien Lin, Henry Sanchez, Razieh Rofougaran, William J. Kaiser. 11-15 [doi]
- A 1.4-GHz 3-mW CMOS LC low phase noise VCO using tapped bond wire inductancesTamara I. Ahrens, Thomas H. Lee. 16-19 [doi]
- A 3.8-mW 2.5-GHz dual-modulus prescaler in a 0.8 µm silicon bipolar production technologyHerbert Knapp, Wilhelm Wilhelm, Mira Rest, Hans-Peter Trost. 20-23 [doi]
- Towards the capability of providing power-area-delay trade-off at the register transfer levelChun-hong Chen, Chi-Ying Tsui. 24-29 [doi]
- Stream synthesis for efficient power simulation based on spectral transformsAlberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi. 30-35 [doi]
- Theoretical bounds for switching activity analysis in finite-state machinesDiana Marculescu, Radu Marculescu, Massoud Pedram. 36-41 [doi]
- Low power salient integration mode image sensor with a low voltage mixed-signal readout architectureEric Y. Chou, A. J. Budrys, Kit M. Cham. 42-47 [doi]
- A delay distribution squeezing scheme with speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) for low voltage LSIsMasayuki Miyazaki, Hiroyuki Mizuno, Koichiro Ishibashi. 48-53 [doi]
- 3D CMOS SOL for high performance computingS. J. Abou-Samra, P. A. Aisa, Alain Guyot, Bernard Courtois. 54-58 [doi]
- A high speed and low power SOL inverter using active body-biasJoonho Gil, Minkyu Je, Jongho Lee, Hyungcheol Shin. 59-63 [doi]
- Power and performance tradeoffs using various caching strategiesR. Iris Bahar, Gianluca Albera, Srilatha Manne. 64-69 [doi]
- Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessorsIbrahim N. Hajj, George D. Stamoulis, Nikolaos Bellas, Constantine D. Polychronopoulos. 70-75 [doi]
- The simulation and evaluation of dynamic voltage scaling algorithmsTrevor Pering, Thomas D. Burd, Robert W. Brodersen. 76-81 [doi]
- Optimizing the DRAM refresh count for merged DRAM/logic LSIsTaku Ohsawa, Koji Kai, Kazuaki Murakami. 82-87 [doi]
- Integrated DC/DC converter with digital controllerFerdinand Sluijs, Kees Hart, Wouter Groeneveld, Stephan Haag. 88-90 [doi]
- CMOS VCOs for frequency synthesis in wireless biotelemetryRafael J. Betancourt-Zamora, Thomas H. Lee. 91-94 [doi]
- The impact of data characteristics and hardware topology on hardware selection for low power DSPGareth Keane, Jonathan Spanier, Roger Woods. 94-96 [doi]
- Low threshold CMOS circuits with low standby currentMircea R. Stan. 97-99 [doi]
- Minimum supply voltage for bulk Si CMOS GSIAzeez J. Bhavnagarwala, Blanca Austin, James D. Meindl. 100-102 [doi]
- 0.5V CMOS logic delivering 200 million 8*8 bit multiplications/s at less than 100 fj based on a 50nm T-gate SOI technologyVolker Dudek, Reinhard Grube, Bernd Höfflinger, Michael Schau. 103-105 [doi]
- Decreasing low-voltage manufacturing-induced delay variations with adaptive mixed-voltage-swing circuitsL. Richard Carley, Akshay Aggarwal, Ram K. Krishnamurthy. 106-108 [doi]
- Power-delay tradeoffs for radix-4 and radix-8 dividersAlberto Nannarelli, Tomás Lang. 109-111 [doi]
- Automatic characterization and modeling of power consumption in static RAMsMauro Chinosi, Roberto Zafalon, Carlo Guardiani. 112-114 [doi]
- Improving sampling efficiency for system level power estimationChih-Shun Ding, Cheng-Ta Hsieh, Massoud Pedram. 115-117 [doi]
- Power invariant vector compaction based on bit clustering and temporal partitioningNicola Dragone, Roberto Zafalon, Carlo Guardiani, Cristina Silvano. 118-120 [doi]
- An empirical comparison of algorithmic, instruction, and architectural power prediction models for high performance embedded DSP processorsCatherine H. Gebotys, Robert J. Gebotys. 121-123 [doi]
- Power calculation and modeling in deep submicronJay Abraham. 124-126 [doi]
- Partial bus-invert coding for power optimization of system level busYoungsoo Shin, Soo-Ik Chae, Kiyoung Choi. 127-129 [doi]
- The petrol approach to high-level power estimationRafael Peset Llopis, Kees G. W. Goossens. 130-132 [doi]
- Power consumption of parallel spread spectrum correlator architecturesWon Namgoong, Teresa H. Y. Meng. 133-135 [doi]
- A low power video processorUzi Zangi, Ran Ginosar. 136-138 [doi]
- Power dissipated by CMOS gates driving lossless transmission linesYehea I. Ismail, Eby G. Friedman, José Luis Neves. 139-142 [doi]
- Emerging power management tools for processor designDavid Blaauw, Abhijit Dharchoudhury, Rajendran Panda, Supamas Sirichotiyakul, Chanhee Oh, Tim Edwards. 143-148 [doi]
- Recent developments in high integration multi-standard CMOS transceivers for personal communication systemsJacques C. Rudell, Jia-Jiunn Ou, R. Sekhar Narayanaswami, George Chien, Jeffrey A. Weldon, Li Lin, King-Chun Tsai, Luns Tee, Kelvin Khoo, Danelle Au, Troy Robinson, Danilo Gerna, Masanori Otsuka, Paul R. Gray. 149-154 [doi]
- Low-energy embedded FPGA structuresEric Kusse, Jan M. Rabaey. 155-160 [doi]
- Low-swing interconnect interface circuitsHui Zhang, Jan M. Rabaey. 161-166 [doi]
- True single-phase energy-recovering logic for low-power, high-speed VLSISuhwan Kim, Marios C. Papaefthymiou. 167-172 [doi]
- System-level power estimation and optimizationLuca Benini, Robin Hodgson, Polly Siegel. 173-178 [doi]
- Memory modeling for system synthesisSari L. Coumeri, Donald E. Thomas. 179-184 [doi]
- Monitoring system activity for OS-directed dynamic power managementLuca Benini, Alessandro Bogliolo, Stefano Cavallucci, Bruno Riccò. 185-190 [doi]
- A reconfigurable dual output low power digital PWM power converterAbram P. Dancy, Anantha Chandrakasan. 191-196 [doi]
- Voltage scheduling problem for dynamically variable voltage processorsTohru Ishihara, Hiroto Yasuura. 197-202 [doi]
- On the optimum design of regulated cascode operational transconductance amplifiersThomas Burger, Qiuting Huang. 203-208 [doi]
- Low power logic synthesis under a general delay modelUnni Narayanan, Peichen Pan, C. L. Liu. 209-214 [doi]
- Local transformation techniques for multi-level logiccircuits utilizing circuit symmetries for power reductionKi-Seok Chung, C. L. Liu. 215-220 [doi]
- A power optimization method considering glitch reduction by gate sizingMasanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru. 221-226 [doi]
- A unified approach in the analysis of latches and flip-flops for low-power systemsVladimir Stojanovic, Vojin G. Oklobdzija, Raminder Singh Bajwa. 227-232 [doi]
- Estimation of maximum power supply noise for deep sub-micron designsYi-Min Jiang, Kwang-Ting Cheng, An-Chang Deng. 233-238 [doi]
- Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacksZhanping Chen, Mark Johnson, Liqiong Wei, Kaushik Roy. 239-244 [doi]
- Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuitsAtila Alvandpour, Per Larsson-Edefors, Christer Svensson. 245-249 [doi]
- Decorrelating (DECOR) transformations for low-power adaptive filtersSumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj. 250-255 [doi]
- The logarithmic number system for strength reduction in adaptive filteringJohn R. Sacha, Mary Jane Irwin. 256-261 [doi]
- Low power architecture of the soft-output Viterbi algorithmDavid Garrett, Mircea R. Stan. 262-267 [doi]
- Low power methodology and design techniques for processor designJ. Patrick Brennan, Alvar Dean, Stephan Kenyon, Sebastian Ventrone. 268-273 [doi]
- Power distribution in high-performance designMichael Benoit, Sandy Taylor, David Overhauser, Steffen Rochel. 274-278 [doi]
- Low-power miniaturized information display systemsMichael Bolotski, Phillip Alvelda. 279-281 [doi]
- Low-power embedded SRAM macros with current-mode read/write operationsJinn-Shyan Wang, Po-Hui Yang, Wayne Tseng. 282-287 [doi]
- A three-port adiabatic register file suitable for embedded applicationsStephan Avery, Marwan A. Jabri. 288-292 [doi]
- A low power SRAM using auto-backgate-controlled MT-CMOSKoji Nii, Hiroshi Makino, Yoshiki Tujihashi, Chikayoshi Morishima, Yasushi Hayakawa, Hiroyuki Nunogami, Takahiko Arakawa, Hisanori Hamano. 293-298 [doi]
- Fast high-level power estimation for control-flow intensive designKamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha. 299-304 [doi]
- The energy complexity of register filesVictor V. Zyuban, Peter M. Kogge. 305-310 [doi]
- Power exploration for dynamic data types through virtual memory management refinementJulio Leao da Silva Jr., Francky Catthoor, Diederik Verkest, Hugo De Man. 311-316 [doi]