Sumant Ramprasad - researchr alias

researchr

You are not signed in
Sign in
Sign up

Viewing Publication 1 - 14 from 14

2016

7.7 A 768Gb 3b/cell 3D-floating-gate NAND flash memoryTomoharu Tanaka, Mark Helm, Tommaso Vali, Ramin Ghodsi, Koichi Kawai, Jae-Kwan Park, Shigekazu Yamada, Feng Pan, Yuichi Einaga, Ali Ghalam, Toru Tanzawa, Jason Guo, Takaaki Ichikawa, Erwin Yu, Satoru Tamada, Tetsuji Manabe, Jiro Kishimoto, Yoko Oikawa, Yasuhiro Takashima, Hidehiko Kuge, Midori Morooka, Ali Mohammadzadeh, Jong Kang, Jeff Tsai, Emanuele Sirizotti, Eric Lee, Luyen Vu, Yuxing Liu, Hoon Choi, Kwonsu Cheon, Daesik Song, Daniel Shin, Jung-Hee Yun, Michele Piccardi, Kim-Fung Chan, Yogesh Luthra, Dheeraj Srinivasan, Srinivasarao Deshmukh, Kalyan Kavalipurapu, Dan Nguyen, Girolamo Gallo, Sumant Ramprasad, Michelle Luo, Qiang Tang, Michele Incarnati, Agostino Macerola, Luigi Pilolli, Luca De Santis, Massimo Rossini, Violante Moschiano, Giovanni Santin, Bernardino Tronca, Hyunseok Lee, Vipul Patel, Ted Pekny, Aaron Yip, Naveen Prabhu, Purval Sule, Trupti Bemalkhedkar, Kiranmayee Upadhyayula, Camila Jaramillo. isscc 2016: 142-144 [doi]

2008

2002

A technique for Improving dual-output domino logicSumant Ramprasad, Ibrahim N. Hajj, Farid N. Najm. tvlsi, 10(4):508-511, 2002. [doi]

1999

Power Estimation and Minimization of Digital Signal Processing SystemsSumant Ramprasad. PhD thesis, University of Illinois Urbana-Champaign, USA, 1999. [doi]

An optimization technique for dual-output domino logicSumant Ramprasad, Ibrahim N. Hajj, Farid N. Najm. islped 1999: 258-260 [doi]

Low-power distributed arithmetic architectures using nonuniform memory partitioningSumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj. iscas 1999: 470-473 [doi]

A coding framework for low-power address and data bussesSumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj. tvlsi, 7(2):212-221, 1999. [doi]

Information-theoretic bounds on average signal transition activity [VLSI systems]Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj. tvlsi, 7(3):359-368, 1999. [doi]

1998

Coding for Low-Power Address and Data Busses: A Source-Coding Framework and ApplicationsSumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj. vlsid 1998: 18-23

Decorrelating (DECOR) transformations for low-power adaptive filtersSumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj. islped 1998: 250-255 [doi]

1997

Achievable bounds on signal transition activitySumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj. iccad 1997: 126-129 [doi]

Analytical Estimation of Transition Activity From Word-Level Signal StatisticsSumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj. dac 1997: 582-587 [doi]

Analytical estimation of signal transition activity from word-level statisticsSumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj. tcad, 16(7):718-733, 1997. [doi]

Sign in or sign up to see more results.

runs on WebDSL