Table of Contents

• A Lightweight Neighbor-Averaging Technique for Reducing Systematic Variations in Physically Unclonable FunctionsAndres Martinez-Sanchez, Deva Borah, Wenjie Che. 1-6 [doi]
• SCIP to the Next Generation of Computing: Extending More than Moore with Silicon Photonics Chiplets in Package (SCIP)Vivek Raghunathan, Karl Muth, Bapiraju Vinnakota, Prasad Venugopal, Rebecca Schaevitz, Manish Mehta. 1-6 [doi]
• Computation of Soft Error Rates Considering Test Pattern SequencesDanushka Senarathna, Spyros Tragoudas. 1-6 [doi]
• AxBy-ViT: Reconfigurable Approximate Computation Bypass for Vision TransformersDongning Ma, Xue-qin, Xun Jiao. 1-5 [doi]
• Model Auto Extraction for Gate-All-Around Silicon Nanowire MOSFETs Using A Decomposition-Based Many-Objective Evolutionary AlgorithmYa-Shu Yang, Yiming Li. 1-6 [doi]
• Pushing Low Power Limits on Multi-Core High Performance SoCVenkateswar Kowkutla, Siva Kothamasu, Kazunobu Shin, Chunhua Hu. 1-4 [doi]
• An Audio Frequency Unfolding Framework for Ultra-Low Sampling Rate SensorsZhihui Gao, Minxue Tang, Ang Li 0005, Yiran Chen. 1-6 [doi]
• A High-Speed CNN Hardware Accelerator with Regular PruningYuan Song, Bi-Wu, Tian Yuan, Weiqiang Liu. 1-5 [doi]
• A Parallel SystemC Virtual Platform for Neuromorphic ArchitecturesMelvin Galicia, Farhad Merchant, Rainer Leupers. 1-6 [doi]
• Thermal Modeling and Design Exploration for Monolithic 3D ICsBaoli Peng, Vasilis F. Pavlidis, Yi-Chung Chen, Yuanqing Cheng. 1-6 [doi]
• Beyond Verilog: Evaluating Chisel versus High-level Synthesis with Tiny DesignsXiangdong Wei, Xinfei Guo. 1 [doi]
• Hardware-aware 3D Model Workload Selection and Characterization for Graphics and ML ApplicationsRuihao Li 0002, Aman Arora, Sikan Li, Qinzhe Wu, Lizy K. John. 1-8 [doi]
• Analysis of the Security Vulnerabilities of 2.5-D and 3-D Integrated CircuitsVaibhav Venugopal Rao, Avesta Sasan, Ioannis Savidis. 1-7 [doi]
• Integrated Sensing and Computing using Energy-Efficient Magnetic SynapsesShaahin Angizi, Arman Roohi. 1-4 [doi]
• Discrete Steps towards Approximate ComputingMichael Gansen, Jie Lou, Florian Freye, Tobias Gemmeke, Farhad Merchant, Albert Zeyer, Mohammad Zeineldeen, Ralf Schlüter, Xin Fan 0002. 1-6 [doi]
• Density Aware Cell Library Design for Design-Technology Co-OptimizationShinichi Nishizawa, Toru Nakura. 1 [doi]
• Reusing Verification Assertions as Security Checkers for Hardware Trojan DetectionMohammad Eslami, Tara Ghasempouri, Samuel Pagliarini. 1-6 [doi]
• Double Deep Q-Learning Based Irrigation and Chemigation ControlJianfeng Song, Dana Porter, Jiang Hu, Thomas H. Marek. 1-6 [doi]
• Multilayered Triboelectric Energy Harvester as a Smart Floor MatFatma Ozudogru, Sercan Koca, Seval Kinden, Shawana Tabassum. 1-4 [doi]
• ReFACE: Efficient Design Methodology for Acceleration of Digital Filter ImplementationsArman Roohi, Shaahin Angizi, Pooriya Navaeilavasani, MohammadReza Taheri. 1-6 [doi]
• i-lete: An IoT-based physical stress monitoring framework for athletesProsenjit Kumar Ghosh, Prabha Sundaravdivel. 1-6 [doi]
• Beta Oscillation Detector Design for Closed-Loop Deep Brain Stimulation of Parkinson's Disease with Memristive Spiking Neural NetworksZachary Kerman, Chunxiu Yu, Hongyu An. 1-6 [doi]
• FPGA-based Reservoir Computing with Optimized Reservoir Node ArchitectureChunxiao Lin, Yibin Liang, Yang Yi. 1-6 [doi]
• Multi-Objective Variation-Aware Sizing for Analog CNFET CircuitsZahra Heshmatpour, Lihong Zhang, Howard M. Heys. 1-6 [doi]
• On Predicting Solution Quality of Maze Routing Using Convolutional Neural NetworkKuei-Huan Chang, Hsin-Hung Pan, Ting-Chi Wang, Po-Yuan Chen, Cindy Chin-Fang Shen. 1-6 [doi]
• HW/SW Codesign for Approximate In-Memory ComputingSimon Thomann, Hong L. G. Nguyen, Hussam Amrouch. 1-6 [doi]
• Lightweight Neural Network Architectures for Resource-Limited DevicesApril L. Reed, Xiaokun Yang, Shi Sha. 1-7 [doi]
• Characterization of mitigation schemes against timing-based side-channel attacks on PCIe hardwareUsman Ali, Salman Abdul Khaliq, Omer Khan. 1-6 [doi]
• Design Methodology for Scalable 2.5D/3D Heterogenous Tiled Chiplet SystemsSrivatsa Rangachar Srinivasa, Jainaveen Sundaram Priya, Dileep Kurian, Erika Ramirez Lozano, Satish Yada, Saransh Chhabra, Kamakhya Prasad Sahu, Paolo A. Aseron, Ronald Kalim, Anuradha Srinivasan, Tanay Karnik. 1-4 [doi]
• Quantum Technology for Comparator CircuitHafiz Md. Hasan Babu, Khandaker Mohammad Mohi Uddin, Rownak Borhan Himel, Nitish Biswas. 1 [doi]
• Hybrid Learning for Orchestrating Deep Learning Inference in Multi-user Edge-cloud NetworksSina Shahhosseini, Tianyi Hu, Dongjoo Seo, Anil Kanduri, Bryan Donyanavard, Amir M. Rahmani, Nikil D. Dutt. 1-6 [doi]
• Large-Scale Logic-Locking Attacks via SimulationRuben Purdy, R. D. Shawn Blanton. 1-6 [doi]
• Peak Prediction Using Multi Layer Perceptron (MLP) for Edge Computing ASICs Targeting Scientific ApplicationsSandeep Miryala, Md. Adnan Zaman, Sandeep Mittal, Yihui Ren, Grzegorz Deptuch, Gabriella Carini, Sioan Zohar, Shinjae Yoo, Jack Fried, Jin Huang, Srinivas Katkoori. 1-6 [doi]
• An IoT-enabled Electronic Textile-based Flexible Body Sensor Network for Real-time Health Monitoring in Assisted Living during PandemicNafize Ishtiaque Hossain, Shawana Tabassum. 1-5 [doi]
• Aperiodic Tasks Scheduling of Energy Harvesting Embedded SystemsHongzhi Xu, Binlian Zhang, Chen Pan. 1-6 [doi]
• Self-timed Sensors for Detecting Static Optical Side Channel AttacksSourav Roy, Tasnuva Farheen, Shahin Tajik, Domenic Forte. 1-6 [doi]
• Layout-based Vulnerability Analysis of LEON3 Processor to Single Event Multiple Transients using Satisfiability Modulo TheoriesSowmith Nethula, Vivek Bansal, Ghaith Bany Hamad, Otmane Aït Mohamed. 1-6 [doi]
• BIC: Blind Identification Countermeasure for Malicious Thermal Sensor Attacks in Mobile SoCsMostafa Abdelrehim, Ahmad Patooghy, Amin Malekmohammadi, Abdel-Hameed A. Badawy. 1-6 [doi]
• Memristor-based Deep Spiking Neural Network with a Computing-In-Memory ArchitectureFabiha Nowshin, Yang Yi. 1-6 [doi]
• An Offline Hardware Security Assessment Approach using Symbol Assertion and Code ShreddingZahra Kazemi, Amin Norollah, Mahdi Fazeli, David Hély, Vincent Beroulle. 1 [doi]
• Stealthy Attack on Algorithmic-Protected DNNs via Smart Bit FlippingBehnam Ghavami, Seyd Movi, Zhenman Fang, Lesley Shannon. 1-7 [doi]
• On the Resiliency of an Analog Memristive Architecture against Adversarial AttacksBijay Raj Paudel, Vasileios Pentsos, Spyros Tragoudas. 1-7 [doi]
• Routability-driven Global Routing with 3D Congestion Estimation Using a Customized Neural NetworkYuxuan Pan, Zhonghua Zhou, André Ivanov. 1-6 [doi]
• Energy Consumption and Runtime Performance Optimizations Applied to Hyperspectral Imaging Cancer DetectionEduardo Juárez, Raquel Lazcano, Daniel Madroñal, César Sanz. 1-8 [doi]
• Sub-Space Modeling: An Enrollment Solution for XOR Arbiter PUF using Machine LearningAmir Ali Pour, David Hély, Vincent Beroulle, Giorgio Di Natale. 1 [doi]
• In-storage Processing of I/O Intensive Applications on Computational Storage DrivesAli Heydarigorji, Mahdi Torabzadehkashi, Siavash Rezaei, Hossein Bobarshad, Vladimir Castro Alves, Pai H. Chou. 1-6 [doi]
• EFCSA: An Efficient Carry Speculative Approximate Adder with RectificationSaurabh Singh, Vishesh Mishra, Sagar Satapathy, Divy Pandey, Kaustav Goswami 0002, Dip Sankar Banerjee, Babita Jajodia. 1-7 [doi]
• An Efficient Approach to Model Strong PUF with Multi-Layer Perceptron using Transfer LearningAmir Ali Pour, David Hély, Vincent Beroulle, Giorgio Di Natale. 1-6 [doi]
• Path-Based Pre-Routing Timing Prediction for Modern Very Large-Scale Integration DesignsLi-Wei Chen, Yao-Nien Sui, Tai-Cheng Lee, Yih-Lang Li, Mango C.-T. Chao, I-Ching Tsai, Tai-Wei Kung, En-Cheng Liu, Yun-Chih Chang. 1-6 [doi]
• Challenges of Securing Low-Power LoRaWAN Devices Deployed in Advanced ManufacturingMohammad Mezanur Rahman Monjur, Joseph Heacock, Joshua Calzadillas, Rui Sun, Qiaoyan Yu. 1 [doi]
• How much is too much error? Analyzing the impact of approximate multipliers on DNNsOurania Spantidi, Iraklis Anagnostopoulos. 1-6 [doi]
• Building Post-layout Performance Model of Analog/RF Circuits by Fine-tuning TechniqueZhikai Wang, Wenfei Hu, Jingbo Zhou, Wenyuan Zhang, Ruitao Wang, Jian Zhang, Dejing Dou, Zuochang Ye, Yan Wang. 1-6 [doi]
• NoC-enabled 3D Heterogeneous Manycore Systems for Big-Data ApplicationsBiresh Kumar Joardar, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty. 1-6 [doi]
• Cross-layer Designs against Non-ideal Effects in ReRAM-based Processing-in-Memory SystemChen Nie, Zongwu Wang, Qidong Tang, Chenyang Lv, Li Jiang 0002, Zhezhi He. 1-6 [doi]
• Examining Vulnerability of HLS-designed Chaskey-12 Circuits to Power Side-Channel AttacksSaya Inagaki, Mingyu Yang, Yang Li, Kazuo Sakiyama, Yuko Hara-Azumi. 1 [doi]
• Joint Optimization of NCL PUF Using Frequency-based Analysis and Evolutionary AlgorithmRabin Yu Acharya, Domenic Forte. 1-6 [doi]
• An Automatic and Efficient BERT Pruning for Edge AI SystemsShaoyi Huang, Ning Liu 0007, Yueying Liang, Hongwu Peng, Hongjia Li, Dongkuan Xu, Mimi Xie, Caiwen Ding. 1-6 [doi]
• LogGen: A Parameterized Generator for Designing Floating-Point Logarithm Units for Deep LearningPragnesh Patel, Aman Arora, Earl E. Swartzlander Jr., Lizy K. John. 1-7 [doi]
• An Intermittent OTA Approach to Update the DL Weights on Energy Harvesting DevicesWei Wei, Sahidul Islam, Jishnu Banerjee, Shanglin Zhou, Chen Pan, Caiwen Ding, Mimi Xie. 1-6 [doi]
• Approximate Decision Trees For Machine Learning Classification on Tiny Printed CircuitsKonstantinos Balaskas, Georgios Zervakis 0001, Kostas Siozios, Mehdi B. Tahoori, Jörg Henkel. 1-6 [doi]
• Low-Precision Quantization Techniques for Hardware-Implementation-Friendly BERT ModelsXinpei Zhang, Yi Ding, Mingfei Yu, Shin-ichi O'Uchi, Masahiro Fujita. 1-6 [doi]
• HPAM: An 8-bit High-Performance Approximate Multiplier Design for Error Resilient ApplicationsDivy Pandey, Vishesh Mishra, Saurabh Singh, Sagar Satapathy, Babita Jajodia, Dip Sankar Banerjee. 1-5 [doi]
• Improving Pin Accessibility of Standard Cell Libraries in 7nm TechnologyTsao-Hsuan Peng, Chih-Chun Hsu, Po-Chun Wang, Rung-Bin Lin. 1-6 [doi]
• Corruption Exposes You: Statistical Key Recovery from Compound Logic LockingArshdeep Kaur, Sayandeep Saha, Chandan Karfa, Debdeep Mukhopadhyay. 1-6 [doi]
• EasyBand2.0: A Framework with Context-Aware Recommendation Mechanism for Safety-Aware Mobility during Pandemic OutbreaksSeema G. Aarella, Ajaya Kumar Tripathy, Saraju P. Mohanty, Elias Kougianos. 1-6 [doi]
• BLCR: Towards Real-time DNN Execution with Block-based Reweighted PruningXiaolong Ma, Geng Yuan, Zhengang Li, Yifan Gong 0004, Tianyun Zhang, Wei Niu, Zheng Zhan 0001, Pu Zhao, Ning Liu 0007, Jian Tang 0008, Xue Lin, Bin Ren, Yanzhi Wang. 1-8 [doi]
• A Unified Statistical Analysis of Comprehensive Fluctuations of Gate-All-Around Silicon Nanosheet MOSFETs Induced by RDF, ITF, and WKF SimultaneouslySekhar Reddy Kola, Yiming Li, Chieh-Yang Chen, Min-Hui Chuang. 1-6 [doi]
• Machine Learning Approach to Characteristic Fluctuation of Bulk FinFETs Induced by Random Interface TrapsRajat Butola, Yiming Li, Sekhar Reddy Kola. 1-6 [doi]
• Joint-optimization of Node Placement and UAV's Trajectory for Self-sustaining Air-Ground IoT systemWen Zhang, Wenlu Wang, Mehdi Sookhak, Chen Pan. 1-6 [doi]
• Strong PUF Security Metrics: Response Sensitivity to Small Challenge PerturbationsFynn Kappelhoff, Rasmus Rasche, Debdeep Mukhopadhyay, Ulrich Rührmair. 1-10 [doi]
• Hardware Trojans for Confidence Reduction and Misclassifications on Neural NetworksMahdieh Grailoo, Mairo Leier, Samuel Pagliarini. 1-6 [doi]
• X-NVDLA: Runtime Accuracy Configurable NVDLA based on Employing Voltage Overscaling ApproachHassan Afzali-Kusha, Massoud Pedram. 7-12 [doi]
• Analysis of the Effect of Off-chip Memory Access on the Performance of an NPU SystemKeonjoo Lee, Donghyun Kang, Duseok Kang, Soonhoi Ha. 13-18 [doi]
• Design and Challenges of Edge Computing ASICs on Front-End ElectronicsSandeep Miryala, Gabriella Carini, Grzegorz Deptuch, Jin Huang, Srinivas Katkoori, Piotr Maj, Soumyajit Mandal, Yihui Ren, Md. Adnan Zaman. 19-27 [doi]
• Low-IR-Drop Test Pattern Regeneration Using A Fast PredictorShi-Tang Liu, Jia-Xian Chen, Yu-Tsung Wu, Chao-Ho Hsieh, Chien-Mo James Li, Norman Chang, Ying Shiun Li, Wentze Chuang. 27-32 [doi]
• Simulation methodology for timing analysis and design optimization in digital superconducting electronicsSam C. Lo, Aaron J. Barker, Stephen R. Whiteley, Eric Mlinar, Jiajun Chen, Dehuang Wu, Kishore Singhal. 33-38 [doi]
• Functional Level Abstraction and Simulation of Verilog-AMS Piecewise Linear ModelsSadia Azam, Nicola Dall'Ora, Enrico Fraccaroli, Franco Fummi. 39-44 [doi]
• Predicting Post-Route Quality of Results Estimates for HLS Designs using Machine LearningPingakshya Goswami, Dinesh Bhatia. 45-50 [doi]
• Investigation on Realistic Stuck-on/off Defects to Complement IEEE P2427 Draft StandardSadia Azam, Nicola Dall'Ora, Enrico Fraccaroli, André Alberts, Renaud Gillon, Franco Fummi. 51-57 [doi]
• Formal Analysis of Integer Multipliers by building Binary Decision Diagram of Adder TreesJitendra Kumar, Asutosh Srivastava, Masahiro Fujita. 58-63 [doi]
• DEEQ: Data-driven End-to-End EQuivalence Checking of High-level SynthesisMohammed Abderehman, Theegala Rakesh Reddy, Chandan Karfa. 64-70 [doi]
• Transaction Level Stimulus Optimization in Functional Verification Using Machine Learning PredictorsSaumil Gogri, Aakash Tyagi, Michael Quinn, Jiang Hu. 71-76 [doi]
• Accelerated Machine Learning for On-Device Hardware-Assisted Cybersecurity in Edge PlatformsHosein Mohammadi Makrani, Zhangying He, Setareh Rafatirad, Hossein Sayadi. 77-83 [doi]
• Does Aging Matter? The Curious Case of Fault Sensitivity AnalysisMohammad Ebrahimabadi, Bijan Fadaeinia, Amir Moradi 0001, Naghmeh Karimi. 84-89 [doi]
• Challenges and Opportunities for Hardware-Assisted Security Improvements in the FieldBenjamin Tan 0001. 90-95 [doi]
• Adaptive-Gravity: A Defense Against Adversarial SamplesAli Mirzaeian, Zhi Tian, Sai Manoj P. D., Banafsheh S. Latibari, Ioannis Savidis, Houman Homayoun, Avesta Sasan. 96-101 [doi]
• An Efficient Error Estimation Technique for Pruning Approximate Data-Flow Graphs in Design Space ExplorationMarzieh Vaeztourshizi, Massoud Pedram. 102-107 [doi]
• A Heterogeneous Solution to the All-pairs Shortest Path Problem using FPGAsMihnea Chirila, Paolo D'Alberto, Hsin-Yu Ting, Alexander V. Veidenbaum, Alexandru Nicolau. 108-113 [doi]
• Integrated Power Delivery Methodology for 3D ICsYousef Safari, Boris Vaisband. 114-119 [doi]
• FastMem: A Fast Architecture-aware Memory Layout DesignAlok Parmar, Kailash Prasad, Nanditha Rao, Joycee Mekie. 120-126 [doi]
• Reinforcement-Learning-based Mixed-Signal IC Placement for Fogging Effect ControlMohammad Hajijafari, Mehrnaz Ahmadi, Zhenxin Zhao, Lihong Zhang. 127-132 [doi]