Babita Jajodia - researchr alias

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Viewing Publication 1 - 9 from 9

2022

FPGA Implementation of Hybrid Karatsuba Multiplications for NIST Post-Quantum Cryptographic Hardware PrimitivesMonalisa Das, Babita Jajodia. isocc 2022: 81-82 [doi]

Hardware Design of Optimized Large Integer Schoolbook Polynomial Multiplications on FPGAMonalisa Das, Babita Jajodia. isocc 2022: 65-66 [doi]

ART-MAC: Approximate Rounding and Truncation based MAC Unit for Fault-Tolerant ApplicationsVishesh Mishra, Divy Pandey, Saurabh Singh, Sagar Satapathy, Kaustav Goswami 0002, Babita Jajodia, Dip Sankar Banerjee. iscas 2022: 1640-1644 [doi]

HPAM: An 8-bit High-Performance Approximate Multiplier Design for Error Resilient ApplicationsDivy Pandey, Vishesh Mishra, Saurabh Singh, Sagar Satapathy, Babita Jajodia, Dip Sankar Banerjee. isqed 2022: 1-5 [doi]

EFCSA: An Efficient Carry Speculative Approximate Adder with RectificationSaurabh Singh, Vishesh Mishra, Sagar Satapathy, Divy Pandey, Kaustav Goswami 0002, Dip Sankar Banerjee, Babita Jajodia. isqed 2022: 1-7 [doi]

Optimized Hardware Implementation of Vedic Binary Multiplier using Nikhilam Sutra on FPGAPalak Yash, Mansi Thakare, Babita Jajodia. lascas 2022: 1-4 [doi]

2021

Efficient Hardware Implementation of Cube Architecture using Yavadunam Sutra on FPGAMansi Thakare, Palak Yash, Debaleena Chakraborty, Babita Jajodia. mwscas 2021: 373-376 [doi]

2018

Mixed-signal demodulator for IEEE 802.15.6 IR-UWB WBAN energy detection-based receiverBabita Jajodia, Anil Mahanta, Shaik Rafi Ahamed. iet-cds, 12(5):523-531, 2018. [doi]

2014

A Six-Segment SRRC Pulse Generator for IEEE 802.15.6 WBAN StandardShaik Rafi Ahamed, Babita Jajodia, Anil Mahanta. bodynets 2014: [doi]

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