Table of Contents

• Temperature Compensation on SRAM-Based Computation in Memory ArrayQibang Zang, Wang Ling Goh, Fei Li 0015, Lu Lu, Anh-Tuan Do. 1-2 [doi]
• Source-Line Shared SOT-MRAM Cell for Energy Efficient Read OperationTaehwan Kim, Jongsun Park. 3-4 [doi]
• SRAM Bit-line Boosting Circuit for Low Latency and Timing Aware Read OperationHyeyeong Lee, Joonhyung Kim, Jongsun Park. 5-6 [doi]
• Bit-Line Decoupled SRAM for Reducing Read Delays in Near Threshold Voltage OperationsHyunchul Park, Jongsun Park. 7-8 [doi]
• Energy-Efficient STT-MRAM based Digital PIM supporting Vertical Computations Using Sense AmplifierYeseul Kim, Jongsun Park. 9-10 [doi]
• Fast-Transient LDO Regulator with RC-less Low-Impedance Buffer and PVT CompensationTzung-Je Lee, Hung-Hsiang Chang. 11-12 [doi]
• A Design of high-efficiency Constant On-Time Control DC-DC Buck Converter for Power Management integrated circuitsQurat-ul Ain, Muhammad Basim, Syed Adil Ali Shah, Kang-Yoon Lee. 13-14 [doi]
• A Fully Differential Switched Capacitor Amplifier with a Two-Stage Folded-Mesh Class AB Operational Amplifier in a 22 nm FD-SOI CMOS ProcessJeongwook Koh, Elmar Herzer. 15-16 [doi]
• Wide Dynamic Range Temperature Sensor Using High Sensitivity PTAT Current GeneratorTzung-Je Lee, Kuo-Hsun Tu. 17-18 [doi]
• A Layout Generator of Latch, Flip-Flop, and Shift Register for High-Speed LinksJunung Choi, Jaeik Cho, Won-Joon Choi, Myungguk Lee, Byungsub Kim. 19-20 [doi]
• An Improved Early Termination Methodology Using Convolutional Neural NetworkSeung-Ho Shin, Hayoung Lee, Sooryeong Lee, Younwoo Yoo, Sungho Kang. 21-22 [doi]
• PROG: Per-Row Output Generator for BOSTSooryeong Lee, Hayoung Lee, Younwoo Yoo, Seung-Ho Shin, Sungho Kang. 23-24 [doi]
• Pair-Grouping Scan Chain Architecture for Multiple Scan Cell Fault DiagnosisSunghoon Kim, Seokjun Jang, Youngki Moon, Sungho Kang. 25-26 [doi]
• FACTGen: Framework for Automated Circuit Topology GeneratorJangwon Suh, Wanyeong Jung. 27-28 [doi]
• Distributed Accumulation based Energy Efficient STT-MRAM based Digital PIM ArchitectureDongsu Kim, Jongsun Park. 29-30 [doi]
• FAME: Fault Address Memory Structure for Repair Time ReductionHayoung Lee, Sooryeong Lee, Younwoo Yoo, Seung-Ho Shin, Sungho Kang. 31-32 [doi]
• Hiding Precharge Operation For Improved SRAM Cycle TimeYoojeong Yang, Dain Chon, Woong Choi. 33-34 [doi]
• High Detection Rate BCH Code with CRC Code for Memory ApplicationMinseo Kim, Jongsun Park. 35-36 [doi]
• YOCO: Unified and Efficient Memory Protection for High Bandwidth MemoryDongwhee Kim, Jungrae Kim. 37-38 [doi]
• Second-order Incremental Delta-sigma Modulator with 3-bit SAR ADC and Capacitor Sharing SchemeWonkyu Do, Neungin Jeon, Hoyong Jung, Young-Chan Jang. 39-40 [doi]
• A 10.12μW 101.98dB-SNDR Three-step Incremental Analog-to-Digital ConverterHuaikun Ji, Zhenhao Fan, Zhaonan Lu, Zhichao Tan, Menglian Zhao. 41-42 [doi]
• An Improved Dynamic Latch Comparator with Low Power Consumption for SAR ADC ApplicationsPhanidarapu Mounika, Deeksha Verma, Kang-Yoon Lee. 43-44 [doi]
• Just-Enough Strategy for Accurate Clock Jitter Measurement Using A Cyclic Time-to-Digital ConverterYung-Chuan Su, Shi-Yu Huang. 45-46 [doi]
• A 8-bit 300MHz Domino Based Successive Approximation Register ADCKo-Chi Kuo, Hsiung-Yu Chi. 47-48 [doi]
• An Energy Efficient Finite State Machine Algorithm for Real-Time Asset Monitoring and Tracking SystemJeongho Lee, Jungkeun Park, Ki-Duk Kim. 49-50 [doi]
• An Accurate and Efficient Stochastic Computing Adder Exploiting Bit Shuffle Control SchemeDonghui Lee, Junhyuk Baik, Yongtae Kim. 51-52 [doi]
• Correlation Aware Random Pattern Generation for Test Time and Shift Power Reduction of Logic BISTJongho Park, Sangjun Lee, Inhwan Lee, Sungwhan Park, Sungho Kang. 53-54 [doi]
• A Method for Implementing LSTM-Based Multiple-People Identification System for Non-Contact Health Monitoring on Small-Scale FPGAMasanao Okamoto, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine. 55-56 [doi]
• A Novel Efficient Approximate Adder Design using Single Input Pair based ComputationHyelin Seok, Hyoju Seo, Jungwon Lee, Yongtae Kim. 57-58 [doi]
• Hardware-Efficient Barrel Shifter Design Using Customized Dynamic Logic Based MUXDain Chon, Yoojeong Yang, Hayoung Choi, Woong Choi. 59-60 [doi]
• Reconfigurable Stochastic Computing Architecture for Computationally Intensive ApplicationsJeongeun Kim, Yue Ri Jeong, Kwonneung Cho, Won-Sik Jeong, Seung Eun Lee. 61-62 [doi]
• Low-Complexity High-Performance Method for Calculating Arbitrary Logarithm FunctionYongzhen Zhang, Yuan Zhang, Yonggang Zhang, Hui Chen 0015. 63-64 [doi]
• Hardware Design of Optimized Large Integer Schoolbook Polynomial Multiplications on FPGAMonalisa Das, Babita Jajodia. 65-66 [doi]
• A Cost-efficient FPGA-based Embedded System for Biosensor PlatformIksu Jang, Jaeyoung Seo, Changjae Moon, Byungsub Kim. 67-68 [doi]
• A Morphological Image-based Recognition of Iron Triad using a Convolutional Neural NetworkEvelyn Q. Raguindin, Reibelle Q. Raguindin, Mark Angelo C. Purio, Ronnie O. Serfa Juan. 69-70 [doi]
• Channel-Wise Activation Map Pruning using Max-Pool for Reducing Memory AccessesHan Cho, Jongsun Park. 71-72 [doi]
• Percentile Clipping based Low Bit-Precision Quantization for Depth Estimation NetworkSeungeon Hwang, Jongsun Park. 73-74 [doi]
• Feature Distribution-based Knowledge Distillation for Deep Neural NetworksHyeonseok Hong, Hyun Kim. 75-76 [doi]
• ApproxTorch: An Approximate Multiplier Evaluation Environment for CNNs based on PytorchKe Ma, Shinji Kimura. 77-78 [doi]
• A 3.65 Gb/s Area-Efficiency ChaCha20 CryptocoreRonaldo Serrano, Marco Sarmiento, Ckristian Duran, Trong-Thuc Hoang, Cong-Kha Pham. 79-80 [doi]
• FPGA Implementation of Hybrid Karatsuba Multiplications for NIST Post-Quantum Cryptographic Hardware PrimitivesMonalisa Das, Babita Jajodia. 81-82 [doi]
• Kyber Accelerator on FPGA Using Energy-Efficient LUT-Based Barrett ReductionDa Won Kim, Dalta Imam Maulana, Wanyeong Jung. 83-84 [doi]
• An Extremely Light-Weight Countermeasure to Power Analysis Attack in Dedicated Circuit for AESYui Koyanagi, Tomoaki Ukezono. 85-86 [doi]
• A Novel Ring Oscillator PUF for FPGA Based on Feedforward Ring OscillatorsTuan-Kiet Dang, Ronaldo Serrano, Trong-Thuc Hoang, Cong-Kha Pham. 87-88 [doi]
• Real-time Implementation of l -key Pose Estimation for Driver Behavior AnalysisMinjoon Kim, Jaehyuk So, Taemin Hwang. 89-90 [doi]
• Backward Graph Construction and Lowering in DL Compiler for Model Training on AI AcceleratorsHyunjeong Kwon, Youngsu Kwon, Jinho Han. 91-92 [doi]
• 2b-tanh: Low Hardware Complexity Activation Functions for LSTMYuan Zhang, Lele Peng, Lianghua Quan, Shubin Zheng, Qiufeng Feng, Yonggang Zhang, Hui Chen 0015. 93-94 [doi]
• An FPGA Implementation of CNN-based Compression Artifact ReductionJaemyung Kim, Jin-Ku Kang, Yongwoo Kim. 95-96 [doi]
• A Layer-wise Training and Pruning Method for Memory Efficient On-chip Learning HardwareDongwoo Lew, Jongsun Park 0001. 97-98 [doi]
• Hardware Analysis of Channel Estimation Method for IRS-Aided MIMO Wireless SystemsJiwon Kim, Seungsik Moon, Youngjoo Lee. 99-100 [doi]
• Smart Computational Resource Distribution System with Automatic Classification Interface for CPSYuuki Teramura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine. 101-102 [doi]
• Data Bus Inversion Encoding for Improving the Power Efficiency of SERDES-Containing Data BusSeongyoon Kang, Jongsun Park. 103-104 [doi]
• Low-Complexity Architecture of Finding First Four Minimum Values for Non-binary LDPC DecodersThang Xuan Pham, Phap Duong-Ngoc, Hanho Lee, Tuy Nguyen Tan. 105-106 [doi]
• An electrical chromatic dispersion emulator using digital signal processingKoki Ando, Yukinaga Shimoda, Daisuke Ito, Makoto Nakamura. 107-108 [doi]
• A Ka band FMCW Transmitter with a High Ratio MultiplierJunho Moon, Sukwon Kang, Dongyeol Yang, Byung-Sung Kim. 109-110 [doi]
• Dual Band Wide Range PLL for IoT ApplicationHo Won Kim, Hun Park, Kang-Yoon Lee. 113-114 [doi]
• D-band Power Amplifier Module with Medium Output Power Using E-plane Waveguide TransitionYoungchae Jeon, Jaehoon Jeong, Yeong Min Jang, Jinho Jeong. 115-116 [doi]
• Tone-based Measurement of Excess Group Delay in Programmable Gain Receiver Chains for RF RangingEalwan Lee. 117-118 [doi]
• Analysis of Impacting Multi-stack Standard Cells on Chip ImplementationKyungjoon Chang, Taewhan Kim. 119-120 [doi]
• Cell-Aware Scan Diagnosis Using Partially Synchronous Set and ResetHyeonchan Lim, Hyojoon Yun, Juyong Lee, Sungho Kang. 121-122 [doi]
• Performance Variability Modeling of Analog Circuits Using Improved Orthogonal Matching PursuitHyunjun Park, Woo-seok Choi. 123-124 [doi]
• Determining PCIe5 Jitter Margin using SIPI Co-SimFern Nee Tan, Li Wern Chew, Ling Li Ong. 125-126 [doi]
• A Novel Processing Unit and Architecture for Process-In Memory (PIM) in NAND Flash MemoryHyunwoo Kim, Seungwon Baek, Jaehong Song, Taigon Song. 127-128 [doi]
• The Quantitative Comparisons of Analog and Digital SRAM Compute-In-Memories for Deep Neural Network ApplicationsJoonhyung Kim, Jongsun Park. 129-130 [doi]
• +T Differential SRAM for Computation-inMemoryJihyung Jung, Youngmin Kim. 131-132 [doi]
• Performance Analysis of a Phase-Change Memory System on Various CNN Inference WorkloadsJihoon Jang, Hyun Kim, Hyokeun Lee. 133-134 [doi]
• Noise-Aware and Lightweight LSTM for Keyword Spotting ApplicationsYingfeng Wang, Yi Sheng Chong, Wang Ling Goh, Anh-Tuan Do. 135-136 [doi]
• A Wide Range Digitally Controlled Oscillator with Direct Proportional Loop ControlYoon Heo, Won Young Lee. 137-138 [doi]
• A 5GHz All-Digital PLL with shunt regulating Ring DCO in BOST for DDR5 ATEKyungmin Baek, Kahyun Kim, Deog Kyoon Jeong. 139-140 [doi]
• Impact of PI Nonlinearity on High-Resolution Frequency-to-Digital ConverterHonggyoo Ahn, Joonghyun Song, Woo-seok Choi. 141-142 [doi]
• A Low-Power Counter-based Digital CDRHyun-In Kim, Jin-Ku Kang. 143-144 [doi]
• A Wide-range Low Power Quarter Rate Single Loop CDRJin-Ho Kim, Jin-Ku Kang. 145-146 [doi]
• Design of Energy Harvesting System with Piezoelectric Device for Onetime-High-Energy ApplicationsYoonho Song, Eunseo Kim, Deog Kyoon Jeong. 149-150 [doi]
• 2T Neuromorphic Device based on oxide semiconductor with High Linearity and Symmetry for High-Precision TrainingSeongmin Park, Gilsu Jeon, Suwon Seong, Yoonyoung Chung. 151-152 [doi]
• A 1.92 μA Always-on ECG Monitoring Mixed-Signal SoC for Implantable Medical ApplicationSyed Muhammad Abubakar, Hanjun Jiang, Yue Yin, Jiahua Shi, Xiaofeng Yang, Wen Jia, Zhihua Wang 0001. 155-156 [doi]
• Design and Test of Computing-In MemoriesJin-Fu Li. 157-158 [doi]
• Design and Dataflow for Multibit SRAM-Based MAC OperationsChuan-Han Cheng, Shih-Hsu Huang, Jin-Fu Li. 159-160 [doi]
• An Aging Detection and Tolerance Framework for 8T SRAM Dot Product CIM EngineYu-Guang Chen, Chi-Hsu Wang, Ing-Chao Lin. 161-162 [doi]
• Layer-wise Exploration of Synaptic Array and Weight Mapping on Heterogeneous Tile-based RRAM CIM ArchitectureHsin-Tzu Wu, Hsin-Yi Pai, Wei-Kai Cheng. 163-164 [doi]
• SVR: A Shard-aware Vertex Reordering Method for Efficient GNN Execution and Memory AccessXingyuan Hu, Zhuang Shao, Chenjia Xie, Li Du, Yuan Du. 165-166 [doi]
• Roadmap for Ferroelectric Memory: Challenges and Opportunities for IMC ApplicationsSourav De, Maximilian Lederer, Yannick Raffel, Franz Müller 0001, Konrad Seidel, Thomas Kämpfe. 167-168 [doi]
• Memory-Centric Fusion-based CNN Accelerator with 3D-NoC and 3D-DRAMWei Lu, Pei-Yu Ge, Po-Tsang Huang, Hung-Ming Chen, Wei Hwang. 169-170 [doi]
• Precision-Aware Workload Distribution and Dataflow for a Hybrid Digital-CIM Deep CNN AcceleratorJui-I Kao, Wei Lu, Po-Tsang Huang, Hung-Ming Chen. 171-172 [doi]
• Lego: Dynamic Tensor-Splitting Multi-Tenant DNN Models on Multi-Chip-Module ArchitectureZhou Yu Xuan, Ching-Jui Lee, Tsung Tai Yeh. 173-174 [doi]
• Dataflow and Hardware Design for The Sharing of Feature MapsDe-Yang Chiu, Shih-Hsu Huang. 175-176 [doi]
• High Accuracy Abnormal ECG Detection Chip Using a Simple Neural NetworkKai-Fen Chang, Yuan-Ho Chen. 177-178 [doi]
• Long-Length Accumulation Unit with Efficient Biasing for Binary Weight CNNsSong-Nien Tang, Chu-Ming Yen. 179-180 [doi]
• A Machine Learning Accelerator for DDoS Attack Detection and Classification on FPGAYu-Kuen Lai, Kai-Po Chang, Xiu-Wen Ku, Hsiang-Lun Hua. 181-182 [doi]
• A Multi-precision Multiply-Accumulation ArrayChaolin Rao, Yueyang Zheng, Haochuan Wan. 183-184 [doi]
• Spiking Neural Networks for digital hand-written number recognitionDian Sheng, Rongxuan Xu, Qinan Wang, Chun Zhao. 185-186 [doi]
• Neuromorphic Hardware Based on Artificial Synaptic DevicesJ. Li, C. Zhao, K. Man. 187-188 [doi]
• Digital Twin based Maximum Power Point Estimation for Photovoltaic SystemsKangshi Wang, Jieming Ma, Jingyi Wang, Bo Xu, Yifan Tao, Ka Lok Man. 189-190 [doi]
• A Long-Term Synchronized System for HealthcareGianfranco Avitabile, Antonello Florio, Ka Lok Man, Chun Zhao. 191-192 [doi]
• Estimating the Angle of Arrival from Multiple RF Sources using Phase InterferometryAntonello Florio, Gianfranco Avitabile, Ka Lok Man. 193-194 [doi]
• An Evaluation of Electricity Demand Forecasting Models for Smart Energy Management SystemsNaoya Kaneko, Koki Iwabuchi, Kenshiro Kato, Daichi Watari, Dafang Zhao, Ittetsu Taniguchi, Hiroki Nishikawa, Takao Onoye. 195-196 [doi]
• Monocular Depth Estimation with Optical Flow Attention for Autonomous DronesTomoyasu Shimhada, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama. 197-198 [doi]
• Joint Generative Network for Abnormal Event Detection in Surveillance VideosSavath Saypadith, Sunepha Detvongsa, Takao Onoye. 199-200 [doi]
• Implementation of AI characteristic motion detecting for improper-photography prevention systemYusuke Inoue, Xiangbo Kong, Takeshi Kumaki. 201-202 [doi]
• Fusing Infrared and Visible Images for DNN-based Nighttime Human DetectionWanyin Shi, Hiroki Matsumiya, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama. 203-204 [doi]
• CNN Acceleration based on Dynamic Pruning and FPGAs ImplementationQi Li, Hengyi Li, Lin Meng. 205-206 [doi]
• Accelerating SoC Security Verification and Vulnerability Detection Through Symbolic ExecutionShibo Tang, Xingxin Wang, Yifei Gao, Wei Hu. 207-208 [doi]
• Towards Automatic Property Generation for SoC Security VerificationXingxin Wang, Shibo Tang, Wei Hu 0008. 209-210 [doi]
• Exploring the high-throughput and low-delay hardware design of SM4 on FPGAYixiao Chen, Jinfeng Song, Shuai Chen, Yuan Cao 0003, Jing Ye, Huawei Li, Xiaowei Li 0001, Xin Lou, Enyi Yao. 211-212 [doi]
• Investigate of Mitigation Solution against Hardware Trojans Attack on Evolvable Hardware PlatformZeYu Li, Zhao Huang, Junjie Wang, Quan Wang. 213-214 [doi]
• A survey and perspective on electronic design automation tools for ensuring SoC securityTian Feng, Haojie Pei, Zhou Jin 0001, Xiao Wu. 215-216 [doi]
• Reinforcement Learning for Hardware Security: Opportunities, Developments, and ChallengesSatwik Patnaik, Vasudev Gohil, Hao Guo, Jeyavijayan (JV) Rajendran. 217-218 [doi]
• 2 WPT System with Relay CoilYota Matsui, Kisara Nakajima, Weisen Luo, Xiuqin Wei. 219-220 [doi]
• Chattering phenomenon in a high-side gate driver circuit using MOSFET equivalent circuitYusuke Goto, Hiroyuki Asahara, Daisuke Ito, Takuji Kousaka. 221-222 [doi]
• Comparative Study of Nonlinear Dynamics in DC-DC Converter with TEMDaiki Hozumi, Shota Uchino, Takuji Kousaka, Hiroyuki Asahara. 223-224 [doi]
• A simple approach of stability analysis and MPPT control in DC-DC converter with TEMYuma Furutani, Takuji Kousaka, Shota Uchino, Hiroyuki Asahara. 225-226 [doi]
• Maximum Efficiency Tracking for Wireless Power Transfer with Multiple ReceiversToshihiro Matsuda, Yutaro Komiyama, Wenqi Zhu, Kien Nguyen, Hiroo Sekiya. 227-228 [doi]
• Performance Comparison of Soiling Detection Using Anomaly Detection MethodologyJunghoon Lee, Chang-Ryeol Jeon, Suk-Ju Kang. 229-230 [doi]
• A High Slew-rate Wide-range Capacitive Load Driving Buffer Amplifier with Correlated Dual Positive Feedback LoopsYoung-Ju Oh, Hyo-Jin Park, Joo-Mi Cho, Hyeon-Ji Choi, Su-Min Park, Chan-Ho Lee, Esun Baik, Chan Kyu Lee, Ho-Chan Ahn, Sung-Wan Hong. 231-232 [doi]
• A 430-MS/s 7-b Asynchronous SAR ADC With a 40 fF Input Sampling CapacitorHyoung-Jung Kim, Jae-Hyuk Lee, Jae-Geun Lim, Jun-Ho Boo, Ho-Jin Kim, Seong-Bo Park, Youngdon Choi, Jung Hwan Choi, Gil-Cho Ahn. 235-236 [doi]
• Miniaturization of bandwidth extension circuit for ESD I/O pad using bridged T-coilJaehoon Jeong, Hyungeun Kim, Jihyeon Lee, Jaehyun Park, Jongsin Shin, Jinho Jeong. 237-238 [doi]
• A Robust and Lightweight Environmental Sound Classification Technique with Adaptation to Microphone for AIoT Sound SensingLujie Peng, Longke Yan, Junyu Yang, Zhiyi Chen, Jun Zhou 0017. 239-240 [doi]
• A Neuromorphic SLAM Accelerator Supporting Multi-Agent Error Correction in Swarm RoboticsJaeHyun Lee, Jong-Hyeok Yoon. 241-242 [doi]
• Network-on-Chip-Centric Accelerator Architectures for Edge AI ComputingBo Wang 0020, Ke Dong, Nurul Akhira Binte Zakaria, Mohit Upadhyay, Weng-Fai Wong, Li-Shiuan Peh. 243-244 [doi]
• A Low-Power Gesture Recognition System utilizing Hybrid Tiny ClassifiersYuncheng Lu, Zehao Li, Xin Zhang, Tony Tae-Hyoung Kim. 245-246 [doi]
• Clustering in Globally Coupled Chaotic Circuits with Changing WeightsYoko Uwate, Yoshifumi Nishio. 247-248 [doi]
• A Mathematical Analysis of Wire Resistance Problem in Memristor CrossbarsGianluca Zoppo, Francesco Marrone, Fernando Corinto, Anil Korkmaz, Su-In Yi, Samuel Palermo, R. Stanley Williams. 249-250 [doi]
• High-speed Serial Interface using PWAM Signaling SchemeHwan-Ung Kim, Jin-Ku Kang. 255-256 [doi]
• An Efficient Systolic Array with Variable Data Precision and Dimension SupportJaehyeon So, Jong Hwan Ko. 257-258 [doi]
• Flexible GPU-Based Implementation of Number Theoretic Transform for Homomorphic EncryptionPhap Duong-Ngoc, Thang Xuan Pham, Hanho Lee, Tuy Nguyen Tan. 259-260 [doi]
• Search-Efficient NAS: Neural Architecture Search for ClassificationAmrita Rana, Kyung Ki Kim. 261-262 [doi]
• Automation Framework for Digital Circuit Design and VerificationHayun Bong, Kyungseon Cho, Yeongkyo Seo. 263-264 [doi]
• Pitch-Shift Effects of an Ergodic Sequential Logic Nonlinear Cochlear Model Induced by Three TonesYui Kishimoto, Hiroyuki Torikai. 265-266 [doi]
• Computation of homoclinic points using particle swarm optimization in 2-dimensional discrete dynamical systemsTatsumi Makino, Yuu Miino, Haruna Matsushita, Takuji Kousaka. 267-268 [doi]
• Time Series Analysis with Noise-Mixing Effects Using Neural NetworksTakuya Nakamura, Ryosuke Shimizu, Yoko Uwate, Yoshufumi Nishio. 269-270 [doi]
• Investigation of the Effect of Adding Random Noise to Noisy Biological Signals on the Classification of Neural NetworkRyosuke Shimizu, Yoko Uwate, Yoshifumi Nishio. 271-272 [doi]
• Multi-point search method for system identification based on chaotic dynamicsMasashi Tomita, Tadashi Tsubone. 273-274 [doi]
• A hardware-efficient sequential logic biochemical switch model toward biosystem simulatorShogo Shirafuji, Hiroyuki Torikai. 275 [doi]
• A hardware-efficient ergodic sequential logic neuron network for brain prosthetic FPGAYuta Shiomi, Hiroyuki Torikai. 276-277 [doi]
• Reduction of Processing Time for Wireless Spiking Neural Network Using Wireless Communication Devices for IoTRyuji Nagazawa, Kien Nguyen, Hiroo Sekiya, Hiroyuki Torikai. 278-279 [doi]
• Synchronization Phenomena of Coupled Oscillators with Node and Edge Weights in Two-Dimensional Complex NetworksKiichi Yamashita, Yoko Uwate, Yoshifumi Nishio. 280-281 [doi]
• Phase Change of Three Coupled Chaotic Circuits to Input SignalsTakahiro Hattori, Yoko Uwate, Yoshifumi Nishio. 282-283 [doi]
• 16 x 10 Pressure Sensor CMOS Driver IC for Resistance Interfence Calibration of CellsJiseong Lee, Seung Soo Kwak, Yun Chan Im, Hyunjin Lee, Yong Sin Kim. 284-285 [doi]
• A Novel Study on a 300°C, High Performance LDO Regulator Using Silicon-On-Insulator Process for Extreme Drill Bit ApplicationChiang Liang Kok. 286-289 [doi]
• STT-MRAM Read and Write Circuit for High Reliability and Power EfficiencyDong-Kil Yun, Jung-Hoon Chun. 290-291 [doi]
• A 80-MHz 91.2 ppm/°C Self-Biased Frequency-Locked-Loop TimerTsung-Ying Chen, Ching-Yuan Yang, Dung-An Wang. 292-293 [doi]
• A Design of SIDITO Buck-Boost Converter with Real Time Maximum Power Point Tracking for RF Energy Harvesting SystemHyun-jin Jeong, Kang-Yoon Lee. 294-297 [doi]
• Capless Low-Dropout Regulator with a Dual Feedback Loop and Voltage DampersYun Seong Lee, Yun Chan Im, Hyunjin Lee, Yong Sin Kim. 298-299 [doi]
• A Three-Level Boost Converter With Peak Current Mode Control for Flying Capacitor Self-BalancingJunho Song, Minsu Kim, Hyung-Min Lee. 300-301 [doi]
• A Programmable Gain Amplifier with Fast Transient Response for Medical Ultrasound SystemMin-Hyeong Son, Young-Chan Lee, Hyun-Min Baek, Hyo-Jeong Choi, Ji-Yong Um. 302-303 [doi]
• A 12.5-Gb/s Switched Capacitor Based Two Tap DFE With High BER PerformanceYosep Cho, Jongmin Park, Jinwook Burm. 304-305 [doi]
• A Power-Efficient Low-Noise Neural Recording Amplifier IC with High Tolerance to Stimulation ArtifactsSoonseong Hong, Hyouk-Kyu Cha. 306-307 [doi]
• Anomaly information detection and fault tolerance control method for CAN-FD bus networkAoran Wang, Jie Fang, Yinan Xu, Yihu Xu, Yubing Wang, Yujing Wu, Jin-Gyun Chung. 308-309 [doi]
• A Biopotential Amplifier IC with Active Common-Mode Cancellation for Closed-Loop Neural InterfacesHyojun Yoo, Hyouk-Kyu Cha. 310-311 [doi]
• Linearity Characterization of Hybrid Driving Scheme for Spatial Light Modulator SystemZ. Di, A. Mani, A. T. Do, A. Baranikov, R. M. Veetil, R. P. Domínguez, A. I. Kuznetsov, K. T. C. Chai. 312-313 [doi]
• Time-Efficient Approximate Stochastic Computing for Medical Imaging ApplicationsKeerthana Pamidimukkala, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi. 314-315 [doi]
• SoC Design for Mobile Real-time Badminton Stroke Classification DesignWen-Hsin Tsai, Kuei-Ann Wen. 316-317 [doi]
• Adaptive Granularity On-die ECCDaero Kim, Jungrae Kim. 318-319 [doi]
• The first study of 10nm-class backside defect using Co-Routine based ETL in DRAMTaesu Shin, Kibum Lee. 320-321 [doi]
• Design of State of Charge and Health Estimation for Li-ion Battery Management SystemMinjoon Kim, Jaehyuk So. 322-323 [doi]
• Low Power Decoder Architecture of Product Code for Storage ControllerSumin Kim, Byungmin Ahn, Bohwan Jun, Mankeun Seo, Hongrak Son, Yong Ho Song. 324-325 [doi]
• A Design and Implementation of MIPI A-PHY RTS LayerSang-Ung Shin, Jin-Ku Kang, Yongwoo Kim. 326-327 [doi]
• Automated Reverse Engineering Tools for FPGA Bitstream Extraction and Logic EstimationMannhee Cho, Dongchan Lee, Sanghyun Lee, Youngmin Kim, Hyung-Min Lee. 328-329 [doi]
• Data extraction from flash memory and reverse engineering using Xilinx 7 series FPGA boardsDongchan Lee, Sanghyun Lee, Mannhee Cho, Hyung-Min Lee, Youngmin Kim. 330-331 [doi]
• Hybrid Assistive Circuit of SRAM for Improving Read and Write Noise Margin in 3nm CMOSJiyoung Lee, Youngmin Kim. 336-337 [doi]
• Memory-Access Optimization for Acceleration and Power Saving of FPGA-Based Image ProcessingShungo Shimohane, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine. 338-339 [doi]
• Releasing the Memory Bottleneck to Display Video CorrectlyHyeonguk Jang, Sukho Lee, Jae-Jin Lee, Kyuseung Han. 340-341 [doi]
• Logic and Reduction Operation based Hardware Trojans in Digital DesignMayukhmali Das, Sounak Dutta, Sayan Chatterjee. 342-343 [doi]
• A Time-Domain Parallel Counter for Deep Learning MacroYixuan He, Minsu Choi, Kyung Ki Kim, Yong-Bin Kim. 346-347 [doi]
• Design Optimization for Decimation Filter for High Performance Sigma-Delta ADCSang-Bo Park, Go-Eun Woo, Hyungwon Kim. 348-349 [doi]
• Implementation of Aurora Interface using SFP+ TransceiverSungkyun Shin, Soyeon Choi, Eunchae Lee, SongYeon Lee, Hoyoung Yoo. 350-351 [doi]
• Low Power Ternary XNOR using 10T SRAM for In-Memory ComputingSanghyun Lee, Youngmin Kim. 352-353 [doi]
• Filter Pruning Method for Inference Time Acceleration Based on YOLOX in Edge DeviceJihun Jeon, Jin-Ku Kang, Yongwoo Kim. 354-355 [doi]
• Exploring GEMM Operations on Different Configurations of the Gemmini AcceleratorDennis Agyemanh Nana Gookyi, Eunchong Lee, KyungHo Kim, Sung-Joon Jang, Sang-Seol Lee. 356-357 [doi]
• Evaluation of Posit Arithmetic on Machine Learning based on Approximate Exponential FunctionsHyun Woo Oh, Won-Sik Jeong, Seung Eun Lee. 358-359 [doi]
• ZOS: Zero Overhead Scan for Systolic Array-based AI acceleratorJihye Kim, Hayoung Lee, Jongho Park, Sunho Kang. 360-361 [doi]
• DNN-based Cancer Recurrence Predictor using FPGAYoung Jun Lim, Do Young Kim, Joon Hyeon Park, Myung Hoon Sunwoo. 362-363 [doi]
• Impact of Oscillator Phase Noise on Time-Domain SNN PerformanceJia Park, Woo-seok Choi. 364-365 [doi]
• Logic Diagnosis Based on Deep Learning for Multiple FaultsTae-Hyun Kim, Hyeonchan Lim, Minho Cheong, Hyojoon Yun, Sungho Kang. 366-367 [doi]
• Lightweighted AI-based Inference using Deterministic Randomness Compensation for Microcontroller ADC Resolution EnhancementJisu Kwon, Daejin Park. 368-369 [doi]
• Clipped Quantization Aware Training for Hardware Friendly Implementation of Image Classification NetworksKyungchul Lee, Jongsun Park 0001. 370-371 [doi]
• Class Difficulty based Mixed Precision Quantization for Low Complexity CNN TrainingJoongho Jo, Jongsun Park 0001. 372-373 [doi]
• Electromagnetic Shielding Effectiveness of Sputtered Non-woven Noise Suppression Sheet with Varied Air GapTakumi Nabeshima, Daisuke Ito, Makoto Nakamura, Takefumi Koyama, Katsunori Muto. 374-375 [doi]
• A 28GHz-band integrated GaAs Power Amplifier for 5G Mobile CommunicationsBonghyuk Park, Hui Dong Lee, Seunghyun Jang, Sunwoo Kong, Seung-Hun Wang, Seok-Bong Hyun. 376-377 [doi]
• A K-band CMOS Power Amplifier with 3-Bit Phase Shifting CharacteristicsHui Dong Lee, Seunghyun Jang, Sunwoo Kong, Bonghyuk Park, Seok-Bong Hyun. 378-379 [doi]
• Modified Wilkinson Power Divider with Resonating Stubs for Physical Isolation of Output PortsYeong Min Jang, Jinho Jeong. 380-381 [doi]
• Enhancement of Emulation Usage for NVMe Solid State DriveJeongbae Seo, Shinbeom Choi, Jaeik Lee, Sekwang Kim, Wooseong Cheong, ByungChul Yoo, Yong Ho Song. 382-383 [doi]
• Toward Heterogeneous Virtual Platforms For Early SW DevelopmentDongyoung Lee, Kyungsu Kang, Jongseong Park, Byunghoon Lee, Jinbeom Kim, Jae-Woo Im. 384-385 [doi]
• High-Level Synthesis Considering Layer Assignment on Timing in 3D-ICMyeongwoo Jin, Doekkeun Oh, Juho Kim. 386-387 [doi]
• Delay Impact on Process Variation of Interconnect throughout technology scalingMyeongwoo Jin, Doekkeun Oh, Juho Kim. 388-389 [doi]
• XSNN: a System-Level Simulator for Spiking Neural Network with Neuron Circuits and Synapse DevicesJeong Woo Min, Jaeha Kim. 390-391 [doi]
• Fast Estimation of NTT/INTT Accelerator Costs for RNS-Based Homomorphic EncryptionGyuhyun Jung, Hyeokjun Kwon, Hyunhoon Lee, Youngjoo Lee. 392-393 [doi]
• Lightweighted Shallow CTS Techniques for Checking Clock Tree Synthesizable Paths in RTL Design TimeNayoung Kwon, Daejin Park. 394-395 [doi]
• A Fast Eye Size Evaluation Method for High Speed SignalHyoseok Song, Kwangmin Kim, Changyoon Han, Byungsub Kim. 396-397 [doi]
• A Highly Linear Digitally Controlled Delay Line with Reduced Duty Cycle DistortionJoonghyun Song, Woo-seok Choi. 398-399 [doi]